Efficient and precise simulation model of synchronization clocks in packet networks

Zdenek Chaloupka, Nayef Alsindi, James Aweya

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

As packet technologies like Ethernet and IP are becoming the dominant in modern telecommunication networks, clock frequency and time synchronization over packet networks is an active area of research. Packet networks are asynchronous by design so frequency and time synchronization with sub-microsecond precision is a demanding task due to packet delay variations. A design of proper algorithms, that meet the telecommunication requirements, usually involves simulations over long period of time with nanoseconds resolution. Such precise and long-term simulation of synchronization performance is challenging, because of the vast amount of computer resources involved. This paper describes a simulation model that is both, efficient and highly precise. The model is able to simulate algorithms behavior over long period of time (tens of hours) while the computation time remains within interval of few minutes.

Original languageBritish English
Title of host publication2013 IEEE 18th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, CAMAD 2013
Pages79-83
Number of pages5
DOIs
StatePublished - 2013
Event2013 IEEE 18th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, CAMAD 2013 - Berlin, Germany
Duration: 25 Sep 201327 Sep 2013

Publication series

Name2013 IEEE 18th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, CAMAD 2013

Conference

Conference2013 IEEE 18th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks, CAMAD 2013
Country/TerritoryGermany
CityBerlin
Period25/09/1327/09/13

Keywords

  • Clocks
  • Frequency synchronization
  • IEEE 1588 PTP
  • Time synchronization

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