TY - GEN

T1 - Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parameters

AU - El-Moselhy, Tarek

AU - Elfadel, I. M.

AU - Widiger, David

PY - 2008

Y1 - 2008

N2 - Recent CAD methodologies of Design-for-Manufacturability (DFM) have naturally led to a significant increase in the number of process and layout parameters that have to be taken into account in design-rule checking. Methodological consistency requires that a similar number of parameters be taken into account during layout parasitic extraction. Because of the inherent variability of these parameters, the issue of efficiently extracting deterministic parasitic sensitivities with respect to such a large number of parameters must be addressed. In this paper, we tackle this very issue in the context of capacitance sensitivity extraction. In particular, we show how the adjoint sensitivity method can be efficiently integrated within a finite-difference (FD) scheme to compute the sensitivity of the capacitance with respect to a large set of BEOL parameters. If np is the number of parameters, the speedup of the adjoint method is shown to be a factor of n p/2 with respect to direct FD sensitivity techniques. The proposed method has been implemented and verified on a 65nm BEOL cross section having 10 metal layers and a total number of 59 parameters. Because of its speed, the method can be advantageously used to prune out of the CAD flow those BEOL parameters that yield a capacitance sensitivity less than a given threshold.

AB - Recent CAD methodologies of Design-for-Manufacturability (DFM) have naturally led to a significant increase in the number of process and layout parameters that have to be taken into account in design-rule checking. Methodological consistency requires that a similar number of parameters be taken into account during layout parasitic extraction. Because of the inherent variability of these parameters, the issue of efficiently extracting deterministic parasitic sensitivities with respect to such a large number of parameters must be addressed. In this paper, we tackle this very issue in the context of capacitance sensitivity extraction. In particular, we show how the adjoint sensitivity method can be efficiently integrated within a finite-difference (FD) scheme to compute the sensitivity of the capacitance with respect to a large set of BEOL parameters. If np is the number of parameters, the speedup of the adjoint method is shown to be a factor of n p/2 with respect to direct FD sensitivity techniques. The proposed method has been implemented and verified on a 65nm BEOL cross section having 10 metal layers and a total number of 59 parameters. Because of its speed, the method can be advantageously used to prune out of the CAD flow those BEOL parameters that yield a capacitance sensitivity less than a given threshold.

KW - Adjoint method

KW - Capacitance extraction

KW - Sensitivity analysis

UR - http://www.scopus.com/inward/record.url?scp=51549110620&partnerID=8YFLogxK

U2 - 10.1109/DAC.2008.4555949

DO - 10.1109/DAC.2008.4555949

M3 - Conference contribution

AN - SCOPUS:51549110620

SN - 9781605581156

T3 - Proceedings - Design Automation Conference

SP - 906

EP - 911

BT - Proceedings of the 45th Design Automation Conference, DAC

T2 - 45th Design Automation Conference, DAC

Y2 - 8 June 2008 through 13 June 2008

ER -