Effect of interface states (Dit) at the a-Si/c-Si interface on the performance of thin film a-Si/c-Si/c-Si heterojunction solar cells

Aaesha Alnuaimi; Ammar Nayfeh

doi:10.1109/PVSC.2012.6317770

Effect of interface states (D_it) at the a-Si/c-Si interface on the performance of thin film a-Si/c-Si/c-Si heterojunction solar cells

Aaesha Alnuaimi
, Ammar Nayfeh

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The effect of interface states (D_it) at the a-Si/c-Si interface on the performance of a-Si(n⁺)/c-Si(p)/c-Si(p⁺) heterojunction solar cells is investigated using Physics Based TCAD simulation. D_it is simulated as Gaussian distribution with peak ranging from 1×10⁹ cm^-2 to 1×10¹⁵ cm ². In addition, c-Si layers of 4, 3, 2, 1, and 0.5 μm are simulated to study the effect of thickness, while the lifetime of the c-Si layer is varied from 1ns to 1ms. For a 2μm c-Si layer with 100μs lifetime, the results show a drop in open-circuit voltage (V_oc) from 0.68 V to 0.52 V as D_it increases from 1×10⁹ cm^-2 to 1×10¹⁵ cm^-2. The efficiency drops from 8% to 6%. The short-circuit current (J_sc) does not change with D_it and is only a function of thickness and lifetime

Original language	British English
Title of host publication	Program - 38th IEEE Photovoltaic Specialists Conference, PVSC 2012
Pages	996-999
Number of pages	4
DOIs	https://doi.org/10.1109/PVSC.2012.6317770
State	Published - 2012
Event	38th IEEE Photovoltaic Specialists Conference, PVSC 2012 - Austin, TX, United States Duration: 3 Jun 2012 → 8 Jun 2012

Publication series

Name	Conference Record of the IEEE Photovoltaic Specialists Conference
ISSN (Print)	0160-8371

Conference

Conference	38th IEEE Photovoltaic Specialists Conference, PVSC 2012
Country/Territory	United States
City	Austin, TX
Period	3/06/12 → 8/06/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Interface States
Lifetime
Photovoltaic Cells
Silicon

Access to Document

10.1109/PVSC.2012.6317770

Cite this

Alnuaimi, A., & Nayfeh, A. (2012). Effect of interface states (D_it) at the a-Si/c-Si interface on the performance of thin film a-Si/c-Si/c-Si heterojunction solar cells. In Program - 38th IEEE Photovoltaic Specialists Conference, PVSC 2012 (pp. 996-999). Article 6317770 (Conference Record of the IEEE Photovoltaic Specialists Conference). https://doi.org/10.1109/PVSC.2012.6317770

@inproceedings{70f0c2e0b21f4db8a709a0a0cab24357,

title = "Effect of interface states (Dit) at the a-Si/c-Si interface on the performance of thin film a-Si/c-Si/c-Si heterojunction solar cells",

abstract = "The effect of interface states (Dit) at the a-Si/c-Si interface on the performance of a-Si(n+)/c-Si(p)/c-Si(p+) heterojunction solar cells is investigated using Physics Based TCAD simulation. Dit is simulated as Gaussian distribution with peak ranging from 1×109 cm-2 to 1×1015 cm 2. In addition, c-Si layers of 4, 3, 2, 1, and 0.5 μm are simulated to study the effect of thickness, while the lifetime of the c-Si layer is varied from 1ns to 1ms. For a 2μm c-Si layer with 100μs lifetime, the results show a drop in open-circuit voltage (Voc) from 0.68 V to 0.52 V as Dit increases from 1×109 cm-2 to 1×1015 cm-2. The efficiency drops from 8\% to 6\%. The short-circuit current (Jsc) does not change with Dit and is only a function of thickness and lifetime",

keywords = "Interface States, Lifetime, Photovoltaic Cells, Silicon",

author = "Aaesha Alnuaimi and Ammar Nayfeh",

year = "2012",

doi = "10.1109/PVSC.2012.6317770",

language = "British English",

isbn = "9781467300643",

series = "Conference Record of the IEEE Photovoltaic Specialists Conference",

pages = "996--999",

booktitle = "Program - 38th IEEE Photovoltaic Specialists Conference, PVSC 2012",

note = "38th IEEE Photovoltaic Specialists Conference, PVSC 2012 ; Conference date: 03-06-2012 Through 08-06-2012",

}

Alnuaimi, A & Nayfeh, A 2012, Effect of interface states (D_it) at the a-Si/c-Si interface on the performance of thin film a-Si/c-Si/c-Si heterojunction solar cells. in Program - 38th IEEE Photovoltaic Specialists Conference, PVSC 2012., 6317770, Conference Record of the IEEE Photovoltaic Specialists Conference, pp. 996-999, 38th IEEE Photovoltaic Specialists Conference, PVSC 2012, Austin, TX, United States, 3/06/12. https://doi.org/10.1109/PVSC.2012.6317770

Effect of interface states (D_it) at the a-Si/c-Si interface on the performance of thin film a-Si/c-Si/c-Si heterojunction solar cells. / Alnuaimi, Aaesha; Nayfeh, Ammar.
Program - 38th IEEE Photovoltaic Specialists Conference, PVSC 2012. 2012. p. 996-999 6317770 (Conference Record of the IEEE Photovoltaic Specialists Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Effect of interface states (Dit) at the a-Si/c-Si interface on the performance of thin film a-Si/c-Si/c-Si heterojunction solar cells

AU - Alnuaimi, Aaesha

AU - Nayfeh, Ammar

PY - 2012

Y1 - 2012

N2 - The effect of interface states (Dit) at the a-Si/c-Si interface on the performance of a-Si(n+)/c-Si(p)/c-Si(p+) heterojunction solar cells is investigated using Physics Based TCAD simulation. Dit is simulated as Gaussian distribution with peak ranging from 1×109 cm-2 to 1×1015 cm 2. In addition, c-Si layers of 4, 3, 2, 1, and 0.5 μm are simulated to study the effect of thickness, while the lifetime of the c-Si layer is varied from 1ns to 1ms. For a 2μm c-Si layer with 100μs lifetime, the results show a drop in open-circuit voltage (Voc) from 0.68 V to 0.52 V as Dit increases from 1×109 cm-2 to 1×1015 cm-2. The efficiency drops from 8% to 6%. The short-circuit current (Jsc) does not change with Dit and is only a function of thickness and lifetime

AB - The effect of interface states (Dit) at the a-Si/c-Si interface on the performance of a-Si(n+)/c-Si(p)/c-Si(p+) heterojunction solar cells is investigated using Physics Based TCAD simulation. Dit is simulated as Gaussian distribution with peak ranging from 1×109 cm-2 to 1×1015 cm 2. In addition, c-Si layers of 4, 3, 2, 1, and 0.5 μm are simulated to study the effect of thickness, while the lifetime of the c-Si layer is varied from 1ns to 1ms. For a 2μm c-Si layer with 100μs lifetime, the results show a drop in open-circuit voltage (Voc) from 0.68 V to 0.52 V as Dit increases from 1×109 cm-2 to 1×1015 cm-2. The efficiency drops from 8% to 6%. The short-circuit current (Jsc) does not change with Dit and is only a function of thickness and lifetime

KW - Interface States

KW - Lifetime

KW - Photovoltaic Cells

KW - Silicon

UR - https://www.scopus.com/pages/publications/84869423591

U2 - 10.1109/PVSC.2012.6317770

DO - 10.1109/PVSC.2012.6317770

M3 - Conference contribution

AN - SCOPUS:84869423591

SN - 9781467300643

T3 - Conference Record of the IEEE Photovoltaic Specialists Conference

SP - 996

EP - 999

BT - Program - 38th IEEE Photovoltaic Specialists Conference, PVSC 2012

T2 - 38th IEEE Photovoltaic Specialists Conference, PVSC 2012

Y2 - 3 June 2012 through 8 June 2012

ER -