Effect of interface states (Dit) at the a-Si/c-Si interface on the performance of thin film a-Si/c-Si/c-Si heterojunction solar cells

Aaesha Alnuaimi, Ammar Nayfeh

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The effect of interface states (Dit) at the a-Si/c-Si interface on the performance of a-Si(n+)/c-Si(p)/c-Si(p+) heterojunction solar cells is investigated using Physics Based TCAD simulation. Dit is simulated as Gaussian distribution with peak ranging from 1×109 cm-2 to 1×1015 cm 2. In addition, c-Si layers of 4, 3, 2, 1, and 0.5 μm are simulated to study the effect of thickness, while the lifetime of the c-Si layer is varied from 1ns to 1ms. For a 2μm c-Si layer with 100μs lifetime, the results show a drop in open-circuit voltage (Voc) from 0.68 V to 0.52 V as Dit increases from 1×109 cm-2 to 1×1015 cm-2. The efficiency drops from 8% to 6%. The short-circuit current (Jsc) does not change with Dit and is only a function of thickness and lifetime

Original languageBritish English
Title of host publicationProgram - 38th IEEE Photovoltaic Specialists Conference, PVSC 2012
Pages996-999
Number of pages4
DOIs
StatePublished - 2012
Event38th IEEE Photovoltaic Specialists Conference, PVSC 2012 - Austin, TX, United States
Duration: 3 Jun 20128 Jun 2012

Publication series

NameConference Record of the IEEE Photovoltaic Specialists Conference
ISSN (Print)0160-8371

Conference

Conference38th IEEE Photovoltaic Specialists Conference, PVSC 2012
Country/TerritoryUnited States
CityAustin, TX
Period3/06/128/06/12

Keywords

  • Interface States
  • Lifetime
  • Photovoltaic Cells
  • Silicon

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