Abstract
I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades [1] (see Fig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown in Fig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade [2], [3]. At the same time, the energy per task has been decreasing at 10-100 X/decade, as shown in Fig. 2, for several systems and system-on-chip subsystems [4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit [5].
| Original language | British English |
|---|---|
| Article number | 8629340 |
| Pages (from-to) | 253-280 |
| Number of pages | 28 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 27 |
| Issue number | 2 |
| DOIs | |
| State | Published - 1 Feb 2019 |
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In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 2, 8629340, 01.02.2019, p. 253-280.
Research output: Contribution to journal › Review article › peer-review
TY - JOUR
T1 - Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory
AU - Alioto, Massimo
AU - Abadir, Magdy S.
AU - Arslan, Tughrul
AU - Boon, Chirn Chye
AU - Burg, Andreas
AU - Chang, Chip Hong
AU - Chang, Meng Fan
AU - Chang, Yao Wen
AU - Chen, Poki
AU - Corsonello, Pasquale
AU - Crovetti, Paolo
AU - Dosho, Shiro
AU - Drechsler, Rolf
AU - Elfadel, Ibrahim Abe M.
AU - Han, Ruonan
AU - Hashimoto, Masanori
AU - Heng, Chun Huat
AU - Heo, Deukhyoun
AU - Ho, Tsung Yi
AU - Homayoun, Houman
AU - Hwang, Yuh Shyan
AU - Joshi, Ajay
AU - Joshi, Rajiv V.
AU - Karnik, Tanay
AU - Kim, Chulwoo
AU - Kim, Tae Hyoung Tony
AU - Kulkarni, Jaydeep
AU - Kursun, Volkan
AU - Lee, Yoonmyung
AU - Li, Hai Helen
AU - Li, Huawei
AU - Mishra, Prabhat
AU - Mohammad, Baker
AU - Kermani, Mehran Mozaffari
AU - Nagata, Makoto
AU - Nii, Koji
AU - Pande, Partha Pratim
AU - Paul, Bipul C.
AU - Pavlidis, Vasilis F.
AU - De Gyvez, Jose Pineda
AU - Savidis, Ioannis
AU - Schaumont, Patrick
AU - Sebastiano, Fabio
AU - Sengupta, Anirban
AU - Seok, Mingoo
AU - Stan, Mircea R.
AU - Tehranipoor, Mark M.
AU - Todri-Sanial, Aida
AU - Verhelst, Marian
AU - Vignoli, Valerio
AU - Wen, Xiaoqing
AU - Xu, Jiang
AU - Zhang, Wei
AU - Zhang, Zhengya
AU - Zhou, Jun
AU - Zwolinski, Mark
AU - Weber, Stacey
N1 - Funding Information: Dr. Burg is a member of the EURASIP SAT SPCN, the IEEE TC-DISPS, and the CAS-VSATC. In 2000, he received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. He was also received the ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a four-year grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship. Along with his students, he received the Best Paper Award from the Journal on Image and Video Processing (EURASIP) in 2013 and the best demo/paper awards at ACSSC 2007, the International Symposium of Circuit and Systems 2013, and ICECS 2013. He serves on the Editorial Board of the Microelectronics Journal (Springer). He has served on the TPC of various conferences on signal processing, communications and VLSI. He was the TPC Co-Chair for VLSI-SoC 2012 and the TCP Co-Chair for ESSCIRC 2016 and SiPS 2017. He is also the General Co-Chair of the International Symposium on Low Power Electronics and Design 2019. Throughout his career, he was involved in the tape-out of more than 35 ASICs. He has served as an Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS in 2013. He is also an Editor of the Journal of Signal Processing Systems (Springer) and Journal of Low Power Electronics and Applications (MDPI). Funding Information: Ruonan Han (S’10–M’14) received the B.Sc. degree in microelectronics from Fudan University, Shanghai, China, in 2007, the M.Sc. degree in electrical engineering from the University of Florida, Gainesville, FL, USA, in 2009, and the Ph.D. degree in electrical and computer engineering from Cornell University, Ithaca, NY, USA, in 2014. In 2012, he was an Intern with Rambus, Inc., Sunnyvale, CA, USA. He is currently an Associate Professor with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT), Cambridge, MA, USA. His current research interests include microelectronic circuits and systems operating at millimeter-wave and terahertz frequencies. Dr. Han is a member of the IEEE Solid-State Circuits Society and the IEEE Microwave Theory and Techniques Society. He was a recipient of the Cornell ECE Director’s Ph.D. Thesis Research Award, the Cornell ECE Innovation Award, and two Best Student Paper Awards of the IEEE Radio-Frequency Integrated Circuits Symposium in 2012 and 2017. He received the IEEE Microwave Theory and Technique Society Graduate Fellowship Award and the IEEE Solid-State Circuits Society Predoctoral Achievement Award. He held MIT E. E. Landsman (1958) Career Development Chair Professorship and received the National Science Foundation CAREER Award in 2017. He is also an Associate Editor of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS and the Guest Editor of the IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. He serves on the Technical Program Committee of the IEEE RFIC Symposium, the IEEE International Microwave Symposium (IMS), and the Steering Committee of IMS in 2019. Funding Information: Deukhyoun Heo received the Ph.D. degree in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2000. In 2000, he joined National Semiconductor Corporation, where he was a Senior Design Engineer involved in the development of silicon RFICs for cellular applications. In 2003, he joined the Faculty of the School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA, USA, where he is currently the Frank Brands Analog Distinguished Professor of Electrical Engineering. He has authored or coauthored approximately 140 publications, including 66 peer-reviewed journal papers and 74 international conference papers. His current research interests include RF/microwave transceiver design based on CMOS, SiGe BiCMOS, and GaAs technologies for wireless and wireline data communications, batteryless wireless sensors and intelligent power management system for sustainable energy sources, adaptive beam formers for phased-array communications, low-power high data-rate wireless links for biomedical applications, and multilayer module development for system-in-package solution. Dr. Heo was a recipient of the 2000 Best Student Paper Award presented at the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) International Microwave Symposium (IMS) and the 2009 National Science Foundation CAREER Award. He has served on the Technical Program Committee of the DATE, IEEE MTT-S IMS, and the International Symposium of Circuit and Systems. He has served as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS from 2007 to 2009 and IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES. Since 2018, he has been serving as an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. Funding Information: Tsung-Yi Ho (SM’12) received the Ph.D. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2005. He is currently a Professor with the Department of Computer Science of National National Tsing Hua University, Hsinchu, Taiwan. His current research interests include design automation and test for microfluidic biochips and neuromorphic computing systems. Dr. Ho was a recipient of the Invitational Fellowship of the Japan Society for the Promotion of Science, the Humboldt Research Fellowship by the Alexander von Humboldt Foundation, the Hans Fischer Fellowship by the Institute of Advanced Study of the Technische Universität München, and the International Visiting Research Scholarship by the Peter Wall Institute of Advanced Study, The University of British Columbia. He received the Best Paper Awards at the VLSI Test Symposium in 2013 and the IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS in 2015. He has served as the Chair of the IEEE Computer Society Tainan Chapter from 2013 to 2015 and the ACM SIGDA Taiwan Chapter from 2014 to 2015. He has served as a Distinguished Visitor of the IEEE Computer Society from 2013 to 2015 and a Distinguished Lecturer of the IEEE Circuits and Systems Society from 2016 to 2017. He is currently serving as an ACM Distinguished Speaker, an Associate Editor for the ACM Journal on Emerging Technologies in Computing Systems, ACM Transactions on Design Automation of Electronic Systems, ACM Transactions on Embedded Computing Systems, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, and IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, and the Guest Editor of the IEEE Design & Test of Computers. He is also serving on the Technical Program Committees of major conferences, including DAC, ICCAD, DATE, ASP-DAC, ISPD, and ICCD. Funding Information: Houman Homayoun received the B.S. degree in electrical engineering from the Sharif University of Technology, Tehran, Iran, in 2003, the M.S. degree in computer engineering from the University of Victoria, Victoria, BC, Canada, in 2005, and the Ph.D. degree from the Department of Computer Science, University of California at Irvine, Irvine, CA, USA, in 2010. He spent two years at the University of California at San Diego, La Jolla, CA, USA, as the National Science Foundation Computing Innovation Fellow awarded by the Computing Research Association and the Computing Community Consortium. He is currently an Associate Professor with the Department of Electrical and Computer Engineering, George Mason University (GMU), Fairfax, VA, USA. He also holds a joint appointment at the Department of Computer Science and the Information Science and Technology Department. He is also the Director of the Accelerated, Secure, and Energy-Efficient Computing Laboratory, GMU. His current research interests include computer security, applied machine learning, big data computing, heterogeneous computing, computer architecture, embedded system design, memory design, DRAM Design, and low-power computing. His research projects of more than $7.2 million have been funded by the National Science Foundation, the General Motors Company, the National Institute of Standards and Technology, the Defense Advanced Research Projects Agency, and the Air Force Research Laboratory. Dr. Homayoun has served as a member of the Advisory Committee, the Cybersecurity Research and Technology Commercialization working group in the Commonwealth of Virginia. He has also served as the Technical Program Committee Member for several international conferences, including ISPASS, DAC, DATE, CODES-ISSS, CASES, FCCM, ICCD, the Great Lakes Symposium on VLSI (GLSVLSI), IGSC, the IEEE International Symposium on Quality Electronic Design (ISQED), the International Symposium on Low Power Electronics and Design, DSD, the Hardware Oriented Security and Trust, IPDPS, and CF. He has served as a Conference Organizing Committee Member for GLSVLSI, ISPASS, GLOBECOM, ISQED, and the IEEE Big Data conferences. He was a recipient of the four-year Computer Science Department, University of California at Irvine, Chair Fellowship. He received the Best Paper Award of the GLSVLSI 2016 Conference. He was the Technical Program Co-Chair of the GLSVLSI 2018. He is currently serving as the General Chair for the GLSVLSI 2019 Conference. He also organized several special sessions and tutorials on the topics of big data computing and heterogeneous architectures in DAC, ICCAD, DATE, CASES, and CODES-ISSS conferences. He is currently serving as an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. Funding Information: Rajiv V. Joshi (M’89–SM’94–F’02) received the B.Tech. degree from IIT Bombay, Mumbai, India, the M.S. degree from the Massachusetts Institute of Technology, Cambridge, MA, USA, and the Dr.Eng.Sc. degree from Columbia University, New York, NY, USA. He is currently a Distinguished Visiting Professor with IIT Roorkee, Roorkee, India. He is also a Research Staff Member and the Key Technical Lead with the T. J. Watson Research Center, IBM. He is also a member of the IBM Academy of Technology. He is also an Industry Liaison for universities as a part of the Semiconductor Research Corporation. His novel interconnects processes and structures for aluminum, tungsten, and copper technologies that are widely used in IBM for various technologies from sub-0.5 µm to 14 nm. He has led successfully predictive failure analytic techniques for yield prediction and also the technology-driven SRAM at the IBM Server Group. He has extensively involved in novel memory designs. He commercialized these techniques. He has authored and coauthored over 200 papers. He holds 60 invention plateaus, 235 U.S. patents, and over 354 international patents. His current research interests include in-memory computation, CNN/DNN accelerators and quantum computing. Dr. Joshi is a fellow of the IEEE International Symposium on Quality Electronic Design and the World Technology Network and a Distinguished Alumnus of the IIT Bombay. He received three Outstanding Technical Achievement, three highest Corporate Patent Portfolio Awards for licensing contributions. He was a recipient of the 2013 IEEE CAS Industrial Pioneer award and the 2013 Mehboob Khan Award from Semiconductor Research Corporation. In 2014, he is inducted into the New Jersey Inventor Hall of Fame along with pioneer Nicola Tesla. He also received the Best Editor Award from the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He was a recipient of the 2015 BMM Award. He received the prestigious IEEE Daniel Noble Award for 2018. He has served as the General Chair for IEEE ISLPED. He has served as a Distinguished Lecturer for IEEE CAS and EDS societies. He has served on the Board of Governors for IEEE CAS as an Industrial Liaison. He will and has served on the committees of AICAS 2019, the International Symposium of Circuit and Systems, the International Symposium on Low Power Electronics and Design (ISLPED), the IEEE VLSI design, the IEEE Custom Integrated Circuits Conference, the IEEE International SOI Conference, ISQED, and the Advanced Metallization Program Committees. He serves as an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He initiated IBM CAS EDS Symposium at IBM in 2017 and will continue into 2018 with AI as the focal area. He is in the Industry Liaison Committee of the IEEE CAS Society. He has given over 45 invited/keynote talks and given several seminars. Funding Information: Hai (Helen) Li (M’08–SM’16–F’19) received the B.S. and M.S. degrees from Tsinghua University, Beijing, China, and the Ph.D. degree from the Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA, in 2004. She was with Qualcomm Inc., San Diego, CA, USA, Intel Corporation, Santa Clara, CA, USA, Seagate Technology, Bloomington, MN, USA, the Polytechnic Institute of New York University, Brooklyn, NY, USA, and the University of Pittsburgh, Pittsburgh, PA, USA. She is currently the Clare Boothe Luce Associate Professor with the Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA. She has authored or coauthored more than 200 technical papers in peer-reviewed journals and conferences and a book Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change (CRC Press, 2011). Her current research interests include neuromorphic architecture for brain-inspired computing systems, machine learning and deep neural network, memory design and architecture, and architecture/circuit/device cross-layer optimization for low power and high performance. Dr. Li was a technical program committee member of over 30 international conference series. She is a Distinguished Member of ACM. She was a recipient of the NSF Career Award, the DARPA Young Faculty Award, and the TUM-IAS Hans Fisher Fellowship from Germany. She received seven best paper awards and additional seven best paper nominations from international conferences. She was the General Chair or the Technical Program Chair of multiple IEEE/ACM conferences. She is currently a Distinguished Lecturer of the IEEE CAS society and a Distinguished Speaker of ACM. She serves as an Associate Editor for the IEEE TCAD, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE TCAS-II, IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, ACM Transactions on Embedded Computing Systems, IEEE CEM, ACM TODAES, and IET CPS. Funding Information: Dr. Mishra’s research has been recognized by several awards, including the NSF CAREER Award from the National Science Foundation, the IBM Faculty Award, three Best Paper Awards (CODES+ISSS 2003, VLSID 2011, and the IEEE International Symposium on Quality Electronic Design 2016) as well as six Best Paper Nominations (DAC 2009, VLSID 2009, DATE 2012, NANOARCH 2013, VLSID 2013, and ASPDAC 2017), and the EDAA Outstanding Dissertation Award from the European Design Automation Association. He currently serves as an Associate Editor for the ACM Transactions on Design Automation of Electronic Systems, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, and the Journal of Electronic Testing. He is currently serving as an ACM Distinguished Speaker. He is also an ACM Distinguished Scientist. Funding Information: Mehran Mozaffari Kermani (S’00–M’11–SM’16) received the B.Sc. degree in electrical and computer engineering from the University of Tehran, Tehran, Iran, in 2005, and the M.E.Sc. and Ph.D. degrees from the Department of Electrical and Computer Engineering, University of Western Ontario, London, ON, Canada, in 2007 and 2011, respectively. He joined Advanced Micro Devices as a Senior ASIC/Layout Designer, where he is integrating sophisticated security/cryptographic capabilities into accelerated processing. In 2012, he joined the Electrical Engineering Department, Princeton University, Princeton, NJ, USA, as an NSERC Postdoctoral Research Fellow. From 2013 to 2017, he was an Assistant Professor with the Rochester Institute of Technology, Rochester, NY, USA. In 2017, he joined the Computer Science and Engineering Department, University of South Florida, Tampa, FL, USA. Dr. Kermani has been the TPC Member for a number of conferences, including Hardware Oriented Security and Trust (Publications Chair), DAC, DATE, RFIDSec, LightSec, WAIFI, FDTC, and DFT. He was a recipient of the prestigious Natural Sciences and Engineering Research Council of Canada Postdoctoral Research Fellowship in 2011 and the Texas Instruments Faculty Award (Douglas Harvey) in 2014. He was the Lead Guest Editor of the IEEE/ACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS and IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING for special issues on security. He has served as the Guest Editor for the IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING for the special issue of Emerging Embedded and Cyber Physical System Security Challenges and Innovations in 2016 and 2017. He is currently serving as an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, ACM Transactions on Embedded Computing Systems, and IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. Funding Information: Dr. Sengupta is an Invited Member of the IEEE CESoc Education and Distinguished Lecturer Nominations Committee. He has been awarded the prestigious IEEE Distinguished Lecturer by the IEEE Consumer Electronics Society in 2017. His research achievements have received wide media coverage as IET International News, U.K., in 2017. He was awarded the Outstanding Associate Editor Award by the IEEE TCVLSI Letter Editorial Board, IEEE Computer Society, in 2017. He is the General/Conference Chair of the 37th IEEE International Symposium on Consumer Electronics (ICCE) 2019, Las Vegas, USA, and the Technical Program Chair of the 15th IEEE International Conference on Information Technology 2016, the 3rd IEEE International Symposium on Nanoelectronic and Information Systems 2017, the 36th IEEE International Conference on Consumer Electronics (ICCE) 2018, Las Vegas, and the 2019 IEEE International Symposium on VLSI, Florida. He has been inducted into the Executive Committee of IEEE Computer Society Technical Committee on VLSI in 2017. His works have been awarded with the IEEE Consumer Electronics Society Best Research Paper Award 2019 at the IEEE CE Society’s Flagship Conference—ICCE 2019, the IEEE Computer Society Technical Committee on VLSI—Best Paper Award at the 2017 IEEE International Symposium on Nanoelectronic and Information Systems, and the IETE Best Research Award by IETE Sub-Center in 2018. He was a recipient of the Visvesvaraya Faculty Research Fellow by Digital India Corporation, Ministry of Electronics & IT. More than a dozen of his IEEE publications have appeared in Top 50 Most Popular Articles with few in Top 5 Most Popular Articles from the IEEE Periodicals. His patents have been cited in industry patents of IBM Corporation, Siemens Corporation, Qualcomm, Amazon Technologies, Siemens, Germany, Mathworks, Inc., Ryerson University, and STC University of Mexico, multiple times. His professional works have received wide media coverage nationally and internationally, such as in IET International News (U.K.), The Times of India, Central Chronicle, DBPOST News, The Free Press Journal, and Dainik Bhaskar. He has supervised more than 15 candidates including several graduated Ph.D. candidates all of whom are/were placed in academia and industry. He has successfully commissioned special issues in the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IET Computers and Digital Techniques, IEEE ACCESS, and IEEE CEM. He was a recipient of the Best Research Paper Award 2017 from IIT Indore. He was awarded the highest rating Excellent by the Department of Science & Technology (DST) based on the performance in funded project in 2017. His ideas have been awarded funding from DST, the Council of Scientific and Industrial Research, and the Department of Electronics & IT. He is the Deputy Editor-in-Chief of the IET Computers & Digital Techniques. He is currently the Editor-in-Chief of the IEEE VLSI CIRCUITS & SYSTEMS LETTER of the IEEE Computer Society TCVLSI. He is currently the Chairman of the IEEE Computer Society TCVLSI. He currently serves in several editorial positions as a Senior Editor, an Associate Editor, an Editor, and the Guest Editor of several IEEE TRANSACTIONS/journals, IET, and Elsevier journals, including the IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE TRANSACTIONS ON CONSUMER ELECTRONICS (to join in 2019), IEEE ACCESS, IET Computer & Digital Techniques, IEEE Consumer Electronics, IEEE CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING, IEEE VLSI CIRCUITS & SYSTEMS LETTER, and Microelectronics Journal (Elsevier). He also serves as the Guest Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS and IET Computers & Digital Techniques. He is a registered Professional Engineer of Ontario. Funding Information: Mingoo Seok (S’05–M’11–SM’18) received the B.S. degree (summa cum laude) in electrical engineering from Seoul National University, Seoul, South Korea, in 2005, and the M.S. and Ph.D. degrees from the University of Michigan at Ann Arbor, Ann Arbor, MI, USA, in 2007 and 2011, respectively, all in electrical engineering. He was a Member of the Technical Staff with Texas Instruments Inc., Dallas, TX, USA, in 2011. Since 2012, he has been with Columbia University, New York, NY, USA, where he is currently an Associate Professor of Electrical Engineering. His current research interests include ultralow-power SoC design for emerging embedded systems, machine-learning VLSI architecture and circuits, variation, voltage, aging, thermal-adaptive circuits and architecture, on-chip integrated power circuits, and nonconventional hardware design. Dr. Seok is the Technical Program Committee Member for several conferences, including the IEEE International Solid-State Circuits Conference (ISSCC) and the IEEE Custom Integrated Circuits Conference (CICC). He received the 1999 Distinguished Undergraduate Scholarship from the Korea Foundation for Advanced Studies, the 2005 Doctoral Fellowship from the Korea Foundation for Advanced Studies, and the 2008 Rackham Pre-Doctoral Fellowship from the University of Michigan. He also received the 2009 AMD/CICC Scholarship Award for picowatt voltage reference work and the 2009 DAC/ISSCC Design Contest for the 35-pW sensor platform design. He also received the 2015 NSF CAREER Award. He has served as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS from 2013 to 2015. He has been serving as an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS since 2015 and IEEE SOLID-STATE CIRCUITS LETTER since 2017. Funding Information: Dr. Verhelst was a member of the ESSCIRC and the International Solid-State Circuits Conference (ISSCC) TPCs and the ISSCC Executive Committee. She was also a member of the Young Academy of Belgium. She is a member of the DATE Conference Executive Committee and the STEM Advisory Committee of the Flemish Government. She currently holds a prestigious ERC Starting Grant from the European Union. She is also an Associate Editor of TCAS-II and JSSC. She is an SSCS Distinguished Lecturer. Funding Information: Dr. Zhang was a recipient of the National Science Foundation CAREER Award in 2011, the Intel Early Career Faculty Award in 2013, the David J. Sakrison Memorial Prize for outstanding doctoral research in electrical engineering and computer sciences from UC Berkeley, and the Best Student Paper Award at the Symposium on VLSI Circuits. He serves on the Program Committees of the Symposium on VLSI Circuits and the IEEE Custom Integrated Circuits Conference. He was also an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS from 2013 to 2015 and IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS from 2014 to 2015. He has been an Associate Editor of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS since 2015. Publisher Copyright: © 1993-2012 IEEE.
PY - 2019/2/1
Y1 - 2019/2/1
N2 - I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades [1] (see Fig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown in Fig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade [2], [3]. At the same time, the energy per task has been decreasing at 10-100 X/decade, as shown in Fig. 2, for several systems and system-on-chip subsystems [4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit [5].
AB - I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades [1] (see Fig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown in Fig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade [2], [3]. At the same time, the energy per task has been decreasing at 10-100 X/decade, as shown in Fig. 2, for several systems and system-on-chip subsystems [4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit [5].
UR - https://www.scopus.com/pages/publications/85061155349
U2 - 10.1109/TVLSI.2018.2886389
DO - 10.1109/TVLSI.2018.2886389
M3 - Review article
AN - SCOPUS:85061155349
SN - 1063-8210
VL - 27
SP - 253
EP - 280
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 2
M1 - 8629340
ER -