TY - GEN
T1 - Double Data Rate Dynamic Edge-Coded Signaling for Low-Power IoT Communication
AU - Muzaffar, Shahzad
AU - Elfadel, Ibrahim Abe M.
N1 - Funding Information:
ACKNOWLEDGMENT This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), Contract 2013 HJ2440, with customized funding from the Mubadala Development Company, Abu Dhabi, UAE.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - Dynamic Edge-Coded Signaling (ECS) is a recently introduced protocol for single-channel signaling between constrained IoT nodes. One of the most distinguishing features of ECS is that its receiver does not require any circuitry for clock-and-data recovery. Other important ECS features include its tolerance with respect to clock variations between transmitter and receiver and its amenability to seamlessly integrate lightweight cryptographic algorithms to ensure secure communication. ECS encodes information using pulse counts with the counting based on one of the pulse edges. In this paper, we address the problem of improving the ECS data rate for a given clock frequency and under a given power envelop by using both pulse edges of the ECS pulse stream. We call the novel protocol double-data-rate ECS (DDR-ECS) in analogy with DDR memory systems. While the concept is intuitive and attractive, its hardware implementation is not. This paper, therefore, presents an efficient hardware design of the DDR-ECS transceiver that preserves the ECS built-in features while essentially doubling the data rate at the same clock frequency and within the same power budget. A 65nm ASIC synthesis of the transceiver shows that DDR-ECS consumes the ECS equivalent power of 19\muW, uses a small form factor of only 1934 gates, and doubles the dynamic data rate to the 7.8-44.4 Mb/s range with an average of 12 Mb/s at a clock rate of 25MHz.
AB - Dynamic Edge-Coded Signaling (ECS) is a recently introduced protocol for single-channel signaling between constrained IoT nodes. One of the most distinguishing features of ECS is that its receiver does not require any circuitry for clock-and-data recovery. Other important ECS features include its tolerance with respect to clock variations between transmitter and receiver and its amenability to seamlessly integrate lightweight cryptographic algorithms to ensure secure communication. ECS encodes information using pulse counts with the counting based on one of the pulse edges. In this paper, we address the problem of improving the ECS data rate for a given clock frequency and under a given power envelop by using both pulse edges of the ECS pulse stream. We call the novel protocol double-data-rate ECS (DDR-ECS) in analogy with DDR memory systems. While the concept is intuitive and attractive, its hardware implementation is not. This paper, therefore, presents an efficient hardware design of the DDR-ECS transceiver that preserves the ECS built-in features while essentially doubling the data rate at the same clock frequency and within the same power budget. A 65nm ASIC synthesis of the transceiver shows that DDR-ECS consumes the ECS equivalent power of 19\muW, uses a small form factor of only 1934 gates, and doubles the dynamic data rate to the 7.8-44.4 Mb/s range with an average of 12 Mb/s at a clock rate of 25MHz.
UR - http://www.scopus.com/inward/record.url?scp=85076814029&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2019.8920318
DO - 10.1109/VLSI-SoC.2019.8920318
M3 - Conference contribution
AN - SCOPUS:85076814029
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
SP - 317
EP - 322
BT - VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings
A2 - Metzler, Carolina
A2 - De Micheli, Giovanni
A2 - Gaillardon, Pierre-Emmanuel
A2 - Silva-Cardenas, Carlos
A2 - Reis, Ricardo
PB - IEEE Computer Society
T2 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019
Y2 - 6 October 2019 through 9 October 2019
ER -