TY - GEN
T1 - Domain-Specific Architecture for IMU Array Data Fusion
AU - Waheed, Owais Talaat
AU - Elfadel, Ibrahim Abe M.
N1 - Funding Information:
ACKNOWLEDGMENT This work is funded by the Mubadala Investment Company, Abu Dhabi, Economic Development Board, Singapore, and GLOBALFOUNDRIES, Singapore under the framework of the MEMS TwinLab program with participation of the A*STAR Institute of Microelectronics, Singapore (IME), Mas-dar Institute at Khalifa University, Abu Dhabi, and GLOBAL-FOUNDRIES, Singapore.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - To achieve high accuracy at low cost in a navigational system, an array of several low-cost MEMS Inertial Measurement Units (IMU's) may be used rather than one single high-performance but high-cost and power hungry mechanical IMU. To combine and predict the outputs and internal states of the IMU array, signal processing algorithms, such as the Kalman Filter (KF), are used with their prediction accuracy increasing with the number of array elements. While large IMU arrays are beneficial for accurate and precise estimation of linear and angular accelerations, they are detrimental to the KF computations since the underlying matrix dimensions of each KF variable increase drastically with array size. This paper discusses a domain-specific processor architecture implemented on an Artix-7 FPGA that can efficiently support the KF matrix operations and improve the throughput of the KF data fusion component. The processor instruction set, design and firmware are discussed in detail. The processor performance and hardware resource utilization are also fully quantified. To constrain the resource and power requirements of the processor-to-array interface, the kinematic model of the IMU accelerometer is used to devise a model-based approximation technique that reduces the number of sensor interface units to just one. This is then implemented using the time multiplexing of the data from various array sensors. Experimental results show that the RMSE of the estimated linear acceleration remains below 0.~3{m}/s^{2} for a sensor noise standard deviation of less than 0.04{m}/s^{2}. The proposed combination of the model-based approximation with the domain specific processor results in a compact data fusion processing system with minimal footprint that vastly outperforms a general purpose processor.
AB - To achieve high accuracy at low cost in a navigational system, an array of several low-cost MEMS Inertial Measurement Units (IMU's) may be used rather than one single high-performance but high-cost and power hungry mechanical IMU. To combine and predict the outputs and internal states of the IMU array, signal processing algorithms, such as the Kalman Filter (KF), are used with their prediction accuracy increasing with the number of array elements. While large IMU arrays are beneficial for accurate and precise estimation of linear and angular accelerations, they are detrimental to the KF computations since the underlying matrix dimensions of each KF variable increase drastically with array size. This paper discusses a domain-specific processor architecture implemented on an Artix-7 FPGA that can efficiently support the KF matrix operations and improve the throughput of the KF data fusion component. The processor instruction set, design and firmware are discussed in detail. The processor performance and hardware resource utilization are also fully quantified. To constrain the resource and power requirements of the processor-to-array interface, the kinematic model of the IMU accelerometer is used to devise a model-based approximation technique that reduces the number of sensor interface units to just one. This is then implemented using the time multiplexing of the data from various array sensors. Experimental results show that the RMSE of the estimated linear acceleration remains below 0.~3{m}/s^{2} for a sensor noise standard deviation of less than 0.04{m}/s^{2}. The proposed combination of the model-based approximation with the domain specific processor results in a compact data fusion processing system with minimal footprint that vastly outperforms a general purpose processor.
UR - https://www.scopus.com/pages/publications/85076813237
U2 - 10.1109/VLSI-SoC.2019.8920380
DO - 10.1109/VLSI-SoC.2019.8920380
M3 - Conference contribution
AN - SCOPUS:85076813237
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
SP - 129
EP - 134
BT - VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings
A2 - Metzler, Carolina
A2 - De Micheli, Giovanni
A2 - Gaillardon, Pierre-Emmanuel
A2 - Silva-Cardenas, Carlos
A2 - Reis, Ricardo
PB - IEEE Computer Society
T2 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019
Y2 - 6 October 2019 through 9 October 2019
ER -