Digital tanlock loop architecture with no delay

Omar Al Kharji Al-Ali, Nader Anani, Saleh Al-Araji, Mahmoud Al-Qutayri, Prasad Ponnapalli

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The π/2 (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional time-delay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using MATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed.

Original languageBritish English
Pages (from-to)179-195
Number of pages17
JournalInternational Journal of Electronics
Issue number2
StatePublished - 1 Feb 2012


  • acquisition
  • jitters
  • locking range
  • no-delay digital tanlock loop
  • phase shifter
  • time-delay digital tanlock loop


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