Digital phase-locked loop for frequency distribution over packet networks

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Abstract

This paper describes a digital phase-locked loop (DPLL) for frequency synchronization over packet networks. This timestamp-based technique for frequency synchronization involves a transmitter clock sending periodically an explicit time indication or timestamp to the receiver so that it can synchronize its local clock to that of the transmitter. The digital oscillator used in the PLL is a divide-by-N counter type oscillator (DNCO). We explain how the DPLL can be designed using standard control theory concepts and show how the loop filter gains are readily obtained given known/specified loop components such as phase detector and DNCO and a set of DPLL performance specifications.

Original languageBritish English
Title of host publicationProceedings
Subtitle of host publicationIECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society
Pages2192-2197
Number of pages6
DOIs
StatePublished - 2011
Event37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011 - Melbourne, VIC, Australia
Duration: 7 Nov 201110 Nov 2011

Publication series

NameIECON Proceedings (Industrial Electronics Conference)

Conference

Conference37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011
Country/TerritoryAustralia
CityMelbourne, VIC
Period7/11/1110/11/11

Keywords

  • Clock Synchronization
  • Digital Controlled Oscillator
  • Divide-by-N counter type oscillator
  • Packet networks
  • Phase-locked loop

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