Design methodology of Multiple-Valued Logic voltage-mode storage circuits

I. Thoidis, D. Soudris, I. Karafyllidis, A. Thanailakis, T. Stouraitis

Research output: Contribution to journalConference articlepeer-review

12 Scopus citations

Abstract

A novel methodology designing for Multiple-Valued Logic voltage-mode storage circuits is introduced. Using the proposed inverter-based unit, uni-signal controlled pass gates and True Single-Phase Clocked Logic-based output units, efficient r-ary (where r is the radix) dynamic and pseudo-static latches can be designed. They exhibit regular, modular, and iterative structure, which means that the for Multiple-Valued Logic circuits are VLSI implementable. Also, these circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode. Since we use only clock signal, additional contribution to low power dissipation of the derived circuits is been made. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.

Original languageBritish English
Pages (from-to)125-128
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
StatePublished - 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: 31 May 19983 Jun 1998

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