Abstract
This paper proposed an asymmetrical 21-level multi-level inverter comprising eight switches and three different rating voltage sources having a ratio of 1:2:7. The three voltage sources are used in different additive and subtractive manners to produce 21 output voltage levels. The level-shifted multi-carrier PWM technique generates gate pulses for the inverter. The theoretical analysis of the inverter is verified using MATLAB/Simulink software. The inverter is simulated under different load and modulation indices under steady-state and dynamic conditions. The inverter produces 5.68 % total harmonic distortion in the output voltage.
| Original language | British English |
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| Title of host publication | 11th International Conference on Power Electronics, Drives and Energy Systems, PEDES 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Edition | 2024 |
| ISBN (Electronic) | 9798350372472 |
| DOIs | |
| State | Published - 2024 |
| Event | 11th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2024 - Mangalore, India Duration: 18 Dec 2024 → 21 Dec 2024 |
Conference
| Conference | 11th IEEE International Conference on Power Electronics, Drives and Energy Systems, PEDES 2024 |
|---|---|
| Country/Territory | India |
| City | Mangalore |
| Period | 18/12/24 → 21/12/24 |
Keywords
- Asymmetrical
- Level-shifted PWM
- Multilevel inverter
- Reduced switch count
- Total harmonic distortion