Delayed Switched Cascode Class-E Amplifier

Nourhan Elsayed; Hani Saleh; Baker Mohammad; Mohammed Ismail; Mihai Sanduleanu

doi:10.1007/978-3-030-92746-2_4

Delayed Switched Cascode Class-E Amplifier

Nourhan Elsayed, Hani Saleh, Baker Mohammad, Mohammed Ismail, Mihai Sanduleanu

Electrical Engineering

Wayne State University

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

Abstract

This chapter discusses the application of a novel switched mode Class-E PA implemented in 22 nm FDSOI technology. The Class-E PA relies on switching not only the input device, but also the cascode device with a 50% duty cycle signal in order to minimize the overlap between the output voltage and the current (pulse injection). Not only will the cascode device be switched, but an added delay element between the input and output transistors is employed. This modification of the delayed phase will result in more control over the power consumption and hence the DE and PAE. This chapter is organized as follows: Sect. 4.1 discusses the switched cascode Class-E PA design and architecture. Followed by Sect. 4.2 that presents the implementation and measurement results. Section 4.3 provides a summary.

Original language	British English
Title of host publication	Analog Circuits and Signal Processing
Publisher	Springer
Pages	31-46
Number of pages	16
DOIs	https://doi.org/10.1007/978-3-030-92746-2_4
State	Published - 2022

Publication series

Name	Analog Circuits and Signal Processing
ISSN (Print)	1872-082X
ISSN (Electronic)	2197-1854

Keywords

Cascode
Class-E
High efficiency
Pulse injection
Switching power amplifier
Tunable transmission line

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10.1007/978-3-030-92746-2_4

Cite this

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abstract = "This chapter discusses the application of a novel switched mode Class-E PA implemented in 22 nm FDSOI technology. The Class-E PA relies on switching not only the input device, but also the cascode device with a 50% duty cycle signal in order to minimize the overlap between the output voltage and the current (pulse injection). Not only will the cascode device be switched, but an added delay element between the input and output transistors is employed. This modification of the delayed phase will result in more control over the power consumption and hence the DE and PAE. This chapter is organized as follows: Sect. 4.1 discusses the switched cascode Class-E PA design and architecture. Followed by Sect. 4.2 that presents the implementation and measurement results. Section 4.3 provides a summary.",

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AB - This chapter discusses the application of a novel switched mode Class-E PA implemented in 22 nm FDSOI technology. The Class-E PA relies on switching not only the input device, but also the cascode device with a 50% duty cycle signal in order to minimize the overlap between the output voltage and the current (pulse injection). Not only will the cascode device be switched, but an added delay element between the input and output transistors is employed. This modification of the delayed phase will result in more control over the power consumption and hence the DE and PAE. This chapter is organized as follows: Sect. 4.1 discusses the switched cascode Class-E PA design and architecture. Followed by Sect. 4.2 that presents the implementation and measurement results. Section 4.3 provides a summary.

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Delayed Switched Cascode Class-E Amplifier

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