Contention-free switch-based implementation of 1024-point radix-2 fourier transform engine

Hani Saleh; Bassam Jamil Mohd; Adnan Aziz; Earl Swartzlander

doi:10.1109/ICCD.2007.4601873

Contention-free switch-based implementation of 1024-point radix-2 fourier transform engine

Hani Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl Swartzlander

Electrical Engineering

University of Texas at Rio Grande Valley

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper examines the use of a switch based architecture to implement a Radix-2 decimation in frequency Fast Fourier Transform Engine. The architecture interconnects M processing elements with 2*M memories. An algorithm to detect and resolve memory access contention is presented. The implementation of 1024-point FFTs with 2 processing elements is discussed in detail, including timing and place-and-route results. The switch based architecture provides a factor of M speedup over a single processing element realization.

Original language	British English
Title of host publication	2007 IEEE International Conference on Computer Design, ICCD 2007
Pages	7-12
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2007.4601873
State	Published - 2007
Event	2007 IEEE International Conference on Computer Design, ICCD 2007 - Lake Tahoe, CA, United States Duration: 7 Oct 2007 → 10 Oct 2007

Publication series

Name	2007 IEEE International Conference on Computer Design, ICCD 2007

Conference

Conference	2007 IEEE International Conference on Computer Design, ICCD 2007
Country/Territory	United States
City	Lake Tahoe, CA
Period	7/10/07 → 10/10/07

Access to Document

10.1109/ICCD.2007.4601873

Cite this

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title = "Contention-free switch-based implementation of 1024-point radix-2 fourier transform engine",

abstract = "This paper examines the use of a switch based architecture to implement a Radix-2 decimation in frequency Fast Fourier Transform Engine. The architecture interconnects M processing elements with 2*M memories. An algorithm to detect and resolve memory access contention is presented. The implementation of 1024-point FFTs with 2 processing elements is discussed in detail, including timing and place-and-route results. The switch based architecture provides a factor of M speedup over a single processing element realization.",

author = "Hani Saleh and Mohd, {Bassam Jamil} and Adnan Aziz and Earl Swartzlander",

year = "2007",

doi = "10.1109/ICCD.2007.4601873",

language = "British English",

isbn = "1424412587",

series = "2007 IEEE International Conference on Computer Design, ICCD 2007",

pages = "7--12",

booktitle = "2007 IEEE International Conference on Computer Design, ICCD 2007",

note = "2007 IEEE International Conference on Computer Design, ICCD 2007 ; Conference date: 07-10-2007 Through 10-10-2007",

}

Saleh, H, Mohd, BJ, Aziz, A & Swartzlander, E 2007, Contention-free switch-based implementation of 1024-point radix-2 fourier transform engine. in 2007 IEEE International Conference on Computer Design, ICCD 2007., 4601873, 2007 IEEE International Conference on Computer Design, ICCD 2007, pp. 7-12, 2007 IEEE International Conference on Computer Design, ICCD 2007, Lake Tahoe, CA, United States, 7/10/07. https://doi.org/10.1109/ICCD.2007.4601873

Contention-free switch-based implementation of 1024-point radix-2 fourier transform engine. / Saleh, Hani; Mohd, Bassam Jamil; Aziz, Adnan et al.
2007 IEEE International Conference on Computer Design, ICCD 2007. 2007. p. 7-12 4601873 (2007 IEEE International Conference on Computer Design, ICCD 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Aziz, Adnan

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AB - This paper examines the use of a switch based architecture to implement a Radix-2 decimation in frequency Fast Fourier Transform Engine. The architecture interconnects M processing elements with 2*M memories. An algorithm to detect and resolve memory access contention is presented. The implementation of 1024-point FFTs with 2 processing elements is discussed in detail, including timing and place-and-route results. The switch based architecture provides a factor of M speedup over a single processing element realization.

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M3 - Conference contribution

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Y2 - 7 October 2007 through 10 October 2007

ER -

Contention-free switch-based implementation of 1024-point radix-2 fourier transform engine

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