Computational-Based Advanced Encryption Standard (AES) Accelerator

Enas Abulibdeh, Hani Saleh, Baker Mohammad, Mahmoud Alqutayri

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


    The demands of high-level security and performance for resource-constrained SoC represent real challenges. Consequently, the dedicated accelerators are designed to deliver a high-quality function with minimal costs. This paper introduces a high-performance Advanced Encryption Standard (AES) accelerator that minimizes the area and power overhead. The suggested design replaces the LUT-based implementation of the substitution block (SBox) with a combinational circuit to break the fixed memory accesses and reduce power consumption. The proposed architecture reduces the hardware complexity by integrating the transformation and its inverse in one block and utilizes one key expansion block. The suggested accelerator outperforms the standard implementation of encryption by 25% and takes the benefits of the design aspects that are utilized in it.

    Original languageBritish English
    Title of host publication2023 International Conference on Microelectronics, ICM 2023
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Number of pages6
    ISBN (Electronic)9798350380828
    StatePublished - 2023
    Event2023 International Conference on Microelectronics, ICM 2023 - Abu Dhabi, United Arab Emirates
    Duration: 17 Nov 202320 Nov 2023

    Publication series

    NameProceedings of the International Conference on Microelectronics, ICM


    Conference2023 International Conference on Microelectronics, ICM 2023
    Country/TerritoryUnited Arab Emirates
    CityAbu Dhabi


    • AES
    • area
    • hybrid block
    • MixColumn
    • performance
    • pipeline
    • power
    • SBox
    • ShiftRow
    • SoC


    Dive into the research topics of 'Computational-Based Advanced Encryption Standard (AES) Accelerator'. Together they form a unique fingerprint.

    Cite this