Comparison of VLSI architectures for a WLAN OFDM transmitter with interpolation filters

Pavlos Kolovos, Eleni Fotopoulou, Thanos Stouraitis

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper introduces two efficient computational techniques for Orthogonal Frequency Division Multiplexing (OFDM) based transmitter design with interpolation filters and discusses the corresponding VLSI architecture issues. The proposed technique is demonstrated by detailing the implementation of a 64-point, radix-24 SDF FFT in combination with digital interpolation filters. By exploiting the redundancy into the cyclic prefix part of the OFDM symbol, the computational load of the transmitter is reduced by approximately 20% for the IEEE 802.11 WLAN standard. The first technique outperforms the second one regarding the number of operations, while the second one is more appealing for applications where required area is an issue.

Original languageBritish English
Title of host publicationICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages451-454
Number of pages4
DOIs
StatePublished - 2007
Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Duration: 11 Dec 200714 Dec 2007

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Country/TerritoryMorocco
CityMarrakech
Period11/12/0714/12/07

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