Compact model parameter extraction using Bayesian inference, incomplete new measurements, and optimal bias selection

Li Yu, Sharad Saxena, Christopher Hess, Ibrahim Abe M. Elfadel, Dimitri A. Antoniadis, Duane S. Boning

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


In this paper, we propose a novel MOSFET parameter extraction method to enable early technology evaluation. The distinguishing feature of the proposed method is that it enables the extraction of MOSFET model parameters using limited and incomplete current-voltage measurements from on-chip monitor circuits. An important step in this method is the use of maximum a posteriori estimation where past measurements of transistors from various technologies are used to learn a prior distribution and its uncertainty matrix for the parameters of the target technology. The framework then utilizes Bayesian inference to facilitate extraction using a very small set of additional measurements. The proposed method is validated using various past technologies and post-silicon measurements for a commercial 28-nm process. The proposed extraction can be used to characterize the statistical variations of MOSFETs with the significant benefit that the restrictions imposed by the backward propagation of variance algorithm are relaxed. We also study the lower bound requirement for the number of transistor measurements needed to extract a full set of parameters for a compact model. Finally, we propose an efficient algorithm for selecting the optimal transistor biases by minimizing a cost function derived from information-theoretic concept of average marginal information gain.

Original languageBritish English
Article number7370807
Pages (from-to)1138-1150
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number7
StatePublished - Jul 2016


  • Bayesian Inference
  • device models
  • parameter extraction


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