Common Mode Voltage Reduction of a Modified Three-Phase Inverter

Recent literature introduces a new three-phase inverter design that includes one 3-level leg and two 2-level legs, aimed at minimizing common mode voltage (CMV) and reducing the number of semiconductor switches. This paper presents a novel simplified pulse-width modulation (PWM) technique specifically developed to further decrease the CMV in this new inverter. The proposed PWM method is experimentally compared against existing PWM technique, as well as the active zero state PWM (AZSPWM) and near state PWM (NSPWM) used in traditional 2-level inverters. Experimental and simulation results indicate that the new PWM technique significantly outperforms existing methods in reducing CMV, highlighting its effectiveness and potential for enhancing inverter performance while maintaining simplicity and reducing hardware complexity.