Clock synchronization for packet networks using a weighted least-squares error filtering technique and enabling circuit emulation service

Circuit emulation service (CES) allows time-division multiplexing (TDM) services (T1/E1 and T3/E3 circuits) to be transparently extended across a packet network. With circuit emulation over IP, for instance, TDM data received from an external device at the edge of an IP network is converted to IP packets, sent through the IP network, passed out of the IP network to its destination, and reassembled into TDM bit stream. Clock synchronization is very important for CES. This paper presents a clock synchronization scheme based on a double exponential filtering technique and a linear process model. The linear process model is used to describe the behaviour of clock synchronization errors between a transmitter and a receiver. In the clock synchronization scheme, the transmitter periodically sends explicit time indications or timestamps to a receiver to enable the receiver to synchronize its local clock to the transmitter's clock. A phase-locked loop (PLL) at the receiver processes the transmitted timestamps to generate timing signal for the receiver. The PLL has a simple implementation and provides both fast responsiveness (i.e. fast acquisition of transmitter frequency at a receiver) and significant jitter reduction in the locked state.