Cache organization for embeded processors; CAM-vs-SRAM

Caches are becoming an increasingly important part of embedded processor design because of the impact they have on performance as well as implementation, specifically, area, power and timing. Different cache organizations make tradeoffs between these metrics. One of the main architectural choices is whether to use standard SRAM-based tag design or to go with a CAMbased organization. This choice has far reaching consequences on all other aspects of the cache design. We will compare these two cache styles using results from a recently completed DSP core design. Our conclusion is that, contrary to popular belief, an SRAM-tag based design provided a more optimal overall design point and is superior in energy respect. Some of driving factors such as the increasing dominance of wire and leakage power will be extrapolated forward to next generation processes.