Cache design for low power and high yield

Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob Abraham

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

23 Scopus citations

Abstract

A novel circuit approach to increase SRAM Static Noise Margin (SNM) and enable lower operating voltage is described. Increasing process variability [1] [2] for new technologies coupled with increased reliability effects like Negative Bias Temperature Instability (NBTI) [3] all contribute to raising the minimum voltage required for stable SRAM. Our strategy is to improve the noise margin of the 6T SRAM cell by reducing the effect of parametric variation of the cell [4], especially in the low voltage operation mode. This is done using a novel circuit that selectively reduces the voltage swing on the world line and reduces the memory supply voltage during write operation. The proposed design increases the SRAM Static Noise Margin (SNM) and write margin using a single voltage supply and with minimum impact to chip area, complexity, and timing. The technique supports both on-chip corner identification to adapt the SRAM behavior to silicon, and software controllability to tradeoff yield, power, and performance.

Original languageBritish English
Title of host publicationProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
Pages103-107
Number of pages5
DOIs
StatePublished - 2008
Event9th International Symposium on Quality Electronic Design, ISQED 2008 - San Jose, CA, United States
Duration: 17 Mar 200819 Mar 2008

Publication series

NameProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Conference

Conference9th International Symposium on Quality Electronic Design, ISQED 2008
Country/TerritoryUnited States
CitySan Jose, CA
Period17/03/0819/03/08

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