Automated flow for generating CMOS custom memory bit map between logical and physical implementation

One of the least popular steps in custom memory design is the tedious task of generating the logical to physical Bit Mapping information. This Bit Mapping information is important for the silicon validation and test engineers to debug failures in the memory blocks on the tester. Historically generating the Bit Mapping document required the designer to manually figure out this mapping and either create a diagram by hand or write a custom script to describe the mapping. This manual process is error prone and hard to validate. For small geometry process technology and big size memory it is important to identify any failing location to facilitate silicon debug. This paper presents an automated flow for generating bit mapping information directly from the physical layout and logical simulations. The flow also generates a graphical interface to identify the location of each memory address. This can be used to identify any potential noise issue (bit flipping) due to interaction between the different memory locations.