TY - GEN
T1 - ASIC Implementation of Associative Memory and Hamming Distance for HDC Application
AU - Hassan, Eman
AU - Tesfai, Huruy
AU - Mohammad, Baker
AU - Saleh, Hani
N1 - Funding Information:
ACKNOWLEDGMENT This publication is based upon work supported by the Khalifa University Competitive Internal Research Award (CIRA) under Award No. [CIRA-2019-026] and System-on-Chip Center Award No. [RC2-2018-020].
Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - Brain-inspired Hyperdimensional computing (HDC) emulates the human brain in the way of memorization, association, and reasoning. At its essence, HDC is about comparing and manipulating vectors of large sizes, making it a good candidate for the realm of AI. In the classification task, associative memory (AM) is responsible for finding the best match between classes hypervectors and query hypervector using Hamming distance (HM) approach. This paper proposes a digital design for the hyperdimensional associative memory (HDAM) main functionality. The DHAM architectures search for the nearest HM and can be scaled linearly to any vector dimension. The design space is explored for 2-options, namely sequential (SDHAM), optimized for the low area but has high latency, and parallel one (PDHAM), optimized for low latency but incur high area. Proven industry-standard ASIC design flow with 65nm foundry technology is used to realize both design and report the power, performance, and area (PPA) results. Our experimental results show that the SDHAM implementation enhances the area and energy by 1.6x and 4.023x compared to the PDHAM design at the latency cost of O(n_{classes}-1). In addition, our results improve the area and energy-delay by 4.6x and 5.6x compared to the state-of-art reports.
AB - Brain-inspired Hyperdimensional computing (HDC) emulates the human brain in the way of memorization, association, and reasoning. At its essence, HDC is about comparing and manipulating vectors of large sizes, making it a good candidate for the realm of AI. In the classification task, associative memory (AM) is responsible for finding the best match between classes hypervectors and query hypervector using Hamming distance (HM) approach. This paper proposes a digital design for the hyperdimensional associative memory (HDAM) main functionality. The DHAM architectures search for the nearest HM and can be scaled linearly to any vector dimension. The design space is explored for 2-options, namely sequential (SDHAM), optimized for the low area but has high latency, and parallel one (PDHAM), optimized for low latency but incur high area. Proven industry-standard ASIC design flow with 65nm foundry technology is used to realize both design and report the power, performance, and area (PPA) results. Our experimental results show that the SDHAM implementation enhances the area and energy by 1.6x and 4.023x compared to the PDHAM design at the latency cost of O(n_{classes}-1). In addition, our results improve the area and energy-delay by 4.6x and 5.6x compared to the state-of-art reports.
KW - Application Specific Integrated Circuit (ASIC)
KW - Associative Memory
KW - Complementary Metal Oxide Semiconductor (CMOS)
KW - Content Addressable memory (CAM)
KW - Encoding
KW - Hyperdimensional Computing
KW - Similarity
UR - http://www.scopus.com/inward/record.url?scp=85124628361&partnerID=8YFLogxK
U2 - 10.1109/ICECS53924.2021.9665633
DO - 10.1109/ICECS53924.2021.9665633
M3 - Conference contribution
AN - SCOPUS:85124628361
T3 - 2021 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021 - Proceedings
BT - 2021 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 28th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2021
Y2 - 28 November 2021 through 1 December 2021
ER -