TY - GEN
T1 - ASIC-Based Implementation of Random Spray Retinex Algorithm for Image Enhancement
AU - Bettayeb, Meriem
AU - Tesfai, Huruy
AU - Mohammad, Baker
AU - Saleh, Hani
N1 - Funding Information:
This publication is based upon work supported by the Khalifa University Competitive Internal Research Award (CIRA) under Award No. [CIRA-2019-026] and [CIRA-2020-053], and System-on-Chip Center Award No. [RC2-2018-020]. *Corresponding author.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This paper presents a detailed digital design for the Random Spray Retinex (RSR) algorithm's main functionality. The proposed hardware architecture supports parallel computing and provides an efficient design in terms of speed, area, and power consumption compared to traditional designs. The implementation results show that the proposed parallel Application Specific Integrated Circuit (ASIC) design is highly efficient in reducing the computational complexity resulting from the data-intensive algorithm while greatly accelerating the RSR algorithm. The proposed method is seen as a step toward a low-complexity, real-Time hardware architecture for the popular retinex algorithm used for image enhancement. Lastly, this architecture was implemented using standard ASIC design flow with 22nm foundry technology; it occupied an area of 430.24 \mu m^{2} and consumed a total power of 66.6 \mu W, for 4 points per spray, making it very suitable for integrated System on Chips (SoC). Furthermore, the design can be scaled to a higher number of points per spray.
AB - This paper presents a detailed digital design for the Random Spray Retinex (RSR) algorithm's main functionality. The proposed hardware architecture supports parallel computing and provides an efficient design in terms of speed, area, and power consumption compared to traditional designs. The implementation results show that the proposed parallel Application Specific Integrated Circuit (ASIC) design is highly efficient in reducing the computational complexity resulting from the data-intensive algorithm while greatly accelerating the RSR algorithm. The proposed method is seen as a step toward a low-complexity, real-Time hardware architecture for the popular retinex algorithm used for image enhancement. Lastly, this architecture was implemented using standard ASIC design flow with 22nm foundry technology; it occupied an area of 430.24 \mu m^{2} and consumed a total power of 66.6 \mu W, for 4 points per spray, making it very suitable for integrated System on Chips (SoC). Furthermore, the design can be scaled to a higher number of points per spray.
KW - ASIC
KW - Image enhancement
KW - Low power digital design
KW - Random Spray Retinex
UR - https://www.scopus.com/pages/publications/85137527821
U2 - 10.1109/MWSCAS54063.2022.9859352
DO - 10.1109/MWSCAS54063.2022.9859352
M3 - Conference contribution
AN - SCOPUS:85137527821
T3 - Midwest Symposium on Circuits and Systems
BT - MWSCAS 2022 - 65th IEEE International Midwest Symposium on Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022
Y2 - 7 August 2022 through 10 August 2022
ER -