Area-time performance of VLSI FIR filter architectures based on residue arithmetic

V. Paliouras; T. Stouraitis

doi:10.1109/EURMIC.1997.617376

Area-time performance of VLSI FIR filter architectures based on residue arithmetic

V. Paliouras, T. Stouraitis

Electrical Engineering

University of Patras

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

The area-time (A/spl middot/T) optimization of a particular class of residue number system (RNS)-based FIR processors is discussed in this paper. To facilitate the optimization procedure, a number of performance models are introduced. Furthermore, moduli bases are attained that lead to RNS FIR filter architectures of minimal A/spl middot/T/sup 2/ product. The A/spl middot/T/sup 2/ performance models include the binary-to-residue and residue-to-binary conversion complexity. In particular, efficient Chinese remainder theorem (CRT) architectures are derived, based on multiply-by-constant units (MCUs), which are systematically designed by an introduced methodology. The A/spl middot/T/sup 2/ performance of the derived residue FIR filter architectures is found to surpass equivalent binary structures under certain conditions.

Original language	British English
Title of host publication	Proceedings - 23rd Euromicro Conference
Subtitle of host publication	New Frontiers of Information Technology, EUROMICRO 1997
Pages	576-583
Number of pages	8
DOIs	https://doi.org/10.1109/EURMIC.1997.617376
State	Published - 1997
Event	23rd EUROMICRO Conference on New Frontiers of Information Technology, EUROMICRO 1997 - Budapest, Hungary Duration: 1 Sep 1997 → 4 Sep 1997

Publication series

Name	Conference Proceedings of the EUROMICRO
ISSN (Print)	1089-6503

Conference

Conference	23rd EUROMICRO Conference on New Frontiers of Information Technology, EUROMICRO 1997
Country/Territory	Hungary
City	Budapest
Period	1/09/97 → 4/09/97

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10.1109/EURMIC.1997.617376

Cite this

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title = "Area-time performance of VLSI FIR filter architectures based on residue arithmetic",

abstract = "The area-time (A/spl middot/T) optimization of a particular class of residue number system (RNS)-based FIR processors is discussed in this paper. To facilitate the optimization procedure, a number of performance models are introduced. Furthermore, moduli bases are attained that lead to RNS FIR filter architectures of minimal A/spl middot/T/sup 2/ product. The A/spl middot/T/sup 2/ performance models include the binary-to-residue and residue-to-binary conversion complexity. In particular, efficient Chinese remainder theorem (CRT) architectures are derived, based on multiply-by-constant units (MCUs), which are systematically designed by an introduced methodology. The A/spl middot/T/sup 2/ performance of the derived residue FIR filter architectures is found to surpass equivalent binary structures under certain conditions.",

author = "V. Paliouras and T. Stouraitis",

year = "1997",

doi = "10.1109/EURMIC.1997.617376",

language = "British English",

isbn = "0818681292",

series = "Conference Proceedings of the EUROMICRO",

pages = "576--583",

booktitle = "Proceedings - 23rd Euromicro Conference",

note = "23rd EUROMICRO Conference on New Frontiers of Information Technology, EUROMICRO 1997 ; Conference date: 01-09-1997 Through 04-09-1997",

}

Paliouras, V & Stouraitis, T 1997, Area-time performance of VLSI FIR filter architectures based on residue arithmetic. in Proceedings - 23rd Euromicro Conference: New Frontiers of Information Technology, EUROMICRO 1997., 617376, Conference Proceedings of the EUROMICRO, pp. 576-583, 23rd EUROMICRO Conference on New Frontiers of Information Technology, EUROMICRO 1997, Budapest, Hungary, 1/09/97. https://doi.org/10.1109/EURMIC.1997.617376

Area-time performance of VLSI FIR filter architectures based on residue arithmetic. / Paliouras, V.; Stouraitis, T.
Proceedings - 23rd Euromicro Conference: New Frontiers of Information Technology, EUROMICRO 1997. 1997. p. 576-583 617376 (Conference Proceedings of the EUROMICRO).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Area-time performance of VLSI FIR filter architectures based on residue arithmetic

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AU - Stouraitis, T.

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AB - The area-time (A/spl middot/T) optimization of a particular class of residue number system (RNS)-based FIR processors is discussed in this paper. To facilitate the optimization procedure, a number of performance models are introduced. Furthermore, moduli bases are attained that lead to RNS FIR filter architectures of minimal A/spl middot/T/sup 2/ product. The A/spl middot/T/sup 2/ performance models include the binary-to-residue and residue-to-binary conversion complexity. In particular, efficient Chinese remainder theorem (CRT) architectures are derived, based on multiply-by-constant units (MCUs), which are systematically designed by an introduced methodology. The A/spl middot/T/sup 2/ performance of the derived residue FIR filter architectures is found to surpass equivalent binary structures under certain conditions.

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Area-time performance of VLSI FIR filter architectures based on residue arithmetic

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