@inproceedings{9632dc4bf59342219a4b50f40e6a9a35,
title = "AQUAIA: A CAD tool for on-chip interconnect modeling, analysis, and optimization",
abstract = "The development of CAD tools for the modeling, analysis, and optimization of on-chip interconnect structures presents many challenges not found in the context of electronic package design and analysis. In this paper, we summarize these challenges and report on a new tool called AQUAIA that addresses them based on the physics of electrical parameter modeling of on-chip interconnects. Specifically, we show how the complexities of on-chip interconnect modeling and analysis can be contained using predefined, representative, three-dimensional signal and power interconnect templates fully compatible with the metal/dielectric back-end-of-the-line (BEOL) stack. These templates enable the fast modeling and simulation of delay, rise/fall time, and crosstalk of signalnets that fully account for the emerging problems of on-chip wiring, including inductive effects and broadband frequency dependence. We also give examples of how to use AQUAIA for interconnect design verification, wiring rule generation, and BEOL process integration.",
author = "Elfadel, {I. M.} and Anand, {M. B.} and A. Deutsch and O. Adekanmbi and M. Angyal and H. Smith and B. Rubin and G. Kopcsay",
note = "Publisher Copyright: {\textcopyright} 2012 IEEE.; 11th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 2002 ; Conference date: 21-10-2002 Through 23-10-2002",
year = "2002",
doi = "10.1109/EPEP.2002.1057945",
language = "British English",
series = "IEEE Topical Meeting on Electrical Performance of Electronic Packaging",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "337--340",
booktitle = "Electrical Performance of Electronic Packaging, EPEP 2002",
address = "United States",
}