Analysis and characterization of leakage reduction methodologies for stacking, body biasing and DLS in 65 nm CMOS technology

This paper presents analysis, characterization and measurement results in a 65 nm CMOS process for different inverter topologies that use various leakage reduction methodologies. The measurement results are carried out to compare the topologies in regards of leakage reduction, active power and speed. Four different methodologies are implemented: standard CMOS, 2-stacked, body biasing, and dynamic logic suppression (DLS). The measurement results indicate that the DLS is an excellent option for ultra-low power IoTs where the leakage is minimized, however, it has a limitation in terms of performance. This makes it suitable for always-on power domain. On the other hand, a standard inverter is a good option for high performance devices but it has the highest leakage which makes it feasible for run fast and stop operation mode. Moreover, stacking and body biasing support low leakage power and moderate performance. The impact of voltage scaling is the best for the DLS where the leakage is saved by 12× at room temperature. Further, the impact of the temperature increases the leakage current for DLS by 3.5× but increases by 13× and 15× for standard and stacking methodologies, respectively.