An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication

Shahzad Muzaffar; Ibrahim (Abe) M. Elfadel

doi:10.1007/978-3-030-23425-6_2

An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication

Shahzad Muzaffar
, Ibrahim (Abe) M. Elfadel

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This chapter presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65 nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31 W and energy efficiency of less than 10 pJ/bit. Finally, this chapter shows how the basic ISA can be extended to include cryptographic features in support of secure IoT communication.

Original language	British English
Title of host publication	VLSI-SoC
Subtitle of host publication	Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Revised and Extended Selected Papers
Editors	Nicola Bombieri, Graziano Pravadelli, Masahiro Fujita, Todd Austin, Ricardo Reis
Pages	14-31
Number of pages	18
DOIs	https://doi.org/10.1007/978-3-030-23425-6_2
State	Published - 2019
Event	26th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2018 - Verona, Italy Duration: 8 Oct 2018 → 10 Oct 2018

Publication series

Name	IFIP Advances in Information and Communication Technology
Volume	561
ISSN (Print)	1868-4238
ISSN (Electronic)	1868-422X

Conference

Conference	26th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2018
Country/Territory	Italy
City	Verona
Period	8/10/18 → 10/10/18

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Clock and data recovery
Domain specific architecture
Dynamic signaling
Instruction set architecture
Internet of things
Low-power communication
Pulsed-Index Communication
Secure communication
Single-channel

Access to Document

10.1007/978-3-030-23425-6_2

OpenUrl availability

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Cite this

Muzaffar, S., & Elfadel, I. M. (2019). An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication. In N. Bombieri, G. Pravadelli, M. Fujita, T. Austin, & R. Reis (Eds.), VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Revised and Extended Selected Papers (pp. 14-31). (IFIP Advances in Information and Communication Technology; Vol. 561). https://doi.org/10.1007/978-3-030-23425-6_2

Muzaffar, Shahzad ; Elfadel, Ibrahim (Abe) M. / An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication. VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Revised and Extended Selected Papers. editor / Nicola Bombieri ; Graziano Pravadelli ; Masahiro Fujita ; Todd Austin ; Ricardo Reis. 2019. pp. 14-31 (IFIP Advances in Information and Communication Technology).

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title = "An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication",

abstract = "This chapter presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65 nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31 W and energy efficiency of less than 10 pJ/bit. Finally, this chapter shows how the basic ISA can be extended to include cryptographic features in support of secure IoT communication.",

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author = "Shahzad Muzaffar and Elfadel, \{Ibrahim (Abe) M.\}",

note = "Funding Information: Acknowledgments. This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), Contract 2013 HJ2440, with customized funding from the Mubadala Development Company, Abu Dhabi, UAE. Publisher Copyright: {\textcopyright} 2019, IFIP International Federation for Information Processing.; 26th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2018 ; Conference date: 08-10-2018 Through 10-10-2018",

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Muzaffar, S & Elfadel, IM 2019, An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication. in N Bombieri, G Pravadelli, M Fujita, T Austin & R Reis (eds), VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology, vol. 561, pp. 14-31, 26th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, 8/10/18. https://doi.org/10.1007/978-3-030-23425-6_2

An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication. / Muzaffar, Shahzad; Elfadel, Ibrahim (Abe) M.
VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Revised and Extended Selected Papers. ed. / Nicola Bombieri; Graziano Pravadelli; Masahiro Fujita; Todd Austin; Ricardo Reis. 2019. p. 14-31 (IFIP Advances in Information and Communication Technology; Vol. 561).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N1 - Funding Information: Acknowledgments. This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), Contract 2013 HJ2440, with customized funding from the Mubadala Development Company, Abu Dhabi, UAE. Publisher Copyright: © 2019, IFIP International Federation for Information Processing.

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N2 - This chapter presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65 nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31 W and energy efficiency of less than 10 pJ/bit. Finally, this chapter shows how the basic ISA can be extended to include cryptographic features in support of secure IoT communication.

AB - This chapter presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65 nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31 W and energy efficiency of less than 10 pJ/bit. Finally, this chapter shows how the basic ISA can be extended to include cryptographic features in support of secure IoT communication.

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KW - Single-channel

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Muzaffar S, Elfadel IM. An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication. In Bombieri N, Pravadelli G, Fujita M, Austin T, Reis R, editors, VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms - 26th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Revised and Extended Selected Papers. 2019. p. 14-31. (IFIP Advances in Information and Communication Technology). doi: 10.1007/978-3-030-23425-6_2

An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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