TY - GEN
T1 - An Instruction Set Architecture for Secure, Low-Power, Dynamic IoT Communication
AU - Muzaffar, Shahzad
AU - Elfadel, Ibrahim (Abe) M.
N1 - Funding Information:
Acknowledgments. This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), Contract 2013 HJ2440, with customized funding from the Mubadala Development Company, Abu Dhabi, UAE.
Publisher Copyright:
© 2019, IFIP International Federation for Information Processing.
PY - 2019
Y1 - 2019
N2 - This chapter presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65 nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31 W and energy efficiency of less than 10 pJ/bit. Finally, this chapter shows how the basic ISA can be extended to include cryptographic features in support of secure IoT communication.
AB - This chapter presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65 nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31 W and energy efficiency of less than 10 pJ/bit. Finally, this chapter shows how the basic ISA can be extended to include cryptographic features in support of secure IoT communication.
KW - Clock and data recovery
KW - Domain specific architecture
KW - Dynamic signaling
KW - Instruction set architecture
KW - Internet of things
KW - Low-power communication
KW - Pulsed-Index Communication
KW - Secure communication
KW - Single-channel
UR - https://www.scopus.com/pages/publications/85068614618
U2 - 10.1007/978-3-030-23425-6_2
DO - 10.1007/978-3-030-23425-6_2
M3 - Conference contribution
AN - SCOPUS:85068614618
SN - 9783030234249
T3 - IFIP Advances in Information and Communication Technology
SP - 14
EP - 31
BT - VLSI-SoC
A2 - Bombieri, Nicola
A2 - Pravadelli, Graziano
A2 - Fujita, Masahiro
A2 - Austin, Todd
A2 - Reis, Ricardo
T2 - 26th IFIP/IEEE WG 10.5 International Conference on Very Large Scale Integration, VLSI-SoC 2018
Y2 - 8 October 2018 through 10 October 2018
ER -
