An Instruction Set Architecture for Low-power, Dynamic IoT Communication

Shahzad Muzaffar; Ibrahim Abe M. Elfadel

doi:10.1109/VLSI-SoC.2018.8644770

An Instruction Set Architecture for Low-power, Dynamic IoT Communication

Shahzad Muzaffar
, Ibrahim Abe M. Elfadel

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31μW and energy efficiency of less than 10pJ/bit.

Original language	British English
Title of host publication	Proceedings of the 2018 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018
Publisher	IEEE Computer Society
Pages	37-42
Number of pages	6
ISBN (Electronic)	9781538647561
DOIs	https://doi.org/10.1109/VLSI-SoC.2018.8644770
State	Published - 19 Feb 2019
Event	26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018 - Verona, Italy Duration: 8 Oct 2018 → 10 Oct 2018

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Volume	2018-October
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018
Country/Territory	Italy
City	Verona
Period	8/10/18 → 10/10/18

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

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10.1109/VLSI-SoC.2018.8644770

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Muzaffar, S., & Elfadel, I. A. M. (2019). An Instruction Set Architecture for Low-power, Dynamic IoT Communication. In Proceedings of the 2018 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018 (pp. 37-42). Article 8644770 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2018-October). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2018.8644770

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abstract = "This paper presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31μW and energy efficiency of less than 10pJ/bit.",

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note = "Funding Information: VII. ACKNOWLEDGEMENT This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), with funding from the Mubadala Development Company, Abu Dhabi, UAE. Publisher Copyright: {\textcopyright} 2018 IEEE.; 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018 ; Conference date: 08-10-2018 Through 10-10-2018",

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Muzaffar, S & Elfadel, IAM 2019, An Instruction Set Architecture for Low-power, Dynamic IoT Communication. in Proceedings of the 2018 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018., 8644770, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, vol. 2018-October, IEEE Computer Society, pp. 37-42, 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, 8/10/18. https://doi.org/10.1109/VLSI-SoC.2018.8644770

An Instruction Set Architecture for Low-power, Dynamic IoT Communication. / Muzaffar, Shahzad; Elfadel, Ibrahim Abe M.
Proceedings of the 2018 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018. IEEE Computer Society, 2019. p. 37-42 8644770 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Muzaffar S, Elfadel IAM. An Instruction Set Architecture for Low-power, Dynamic IoT Communication. In Proceedings of the 2018 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018. IEEE Computer Society. 2019. p. 37-42. 8644770. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC.2018.8644770

An Instruction Set Architecture for Low-power, Dynamic IoT Communication

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