TY - GEN
T1 - An Instruction Set Architecture for Low-power, Dynamic IoT Communication
AU - Muzaffar, Shahzad
AU - Elfadel, Ibrahim Abe M.
N1 - Funding Information:
VII. ACKNOWLEDGEMENT This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), with funding from the Mubadala Development Company, Abu Dhabi, UAE.
Publisher Copyright:
© 2018 IEEE.
PY - 2019/2/19
Y1 - 2019/2/19
N2 - This paper presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31μW and energy efficiency of less than 10pJ/bit.
AB - This paper presents an instruction set architecture (ISA) dedicated to the rapid and efficient implementation of single-channel IoT communication interfaces. The architecture is meant to provide a programming interface for the implementation of signaling protocols based on the recently introduced pulsed-index schemes. In addition to the traditional aspects of ISA design such as addressing modes, instruction types, instruction formats, registers, interrupts, and external I/O, the ISA includes special-purpose instructions that facilitate bit stream encoding and decoding based on the pulsed-index techniques. Verilog HDL is used to synthesize a fully functional processor based on this ISA and provide both an FPGA implementation and a synthesised ASIC design in GLOBALFOUNDRIES 65nm. The ASIC design confirms the low-power features of this ISA with consumed power around 31μW and energy efficiency of less than 10pJ/bit.
UR - http://www.scopus.com/inward/record.url?scp=85063028391&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2018.8644770
DO - 10.1109/VLSI-SoC.2018.8644770
M3 - Conference contribution
AN - SCOPUS:85063028391
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
SP - 37
EP - 42
BT - Proceedings of the 2018 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018
PB - IEEE Computer Society
T2 - 26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018
Y2 - 8 October 2018 through 10 October 2018
ER -
