An FPGA implementation of NIST 256 prime field ECC processor

H. Marzouqi, M. Al-Qutayri, K. Salah

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

30 Scopus citations

Abstract

In this paper, we propose a new Application Specific Instruction-set (ASIP) ECC processor based on Redundant Signed Digit representation with a novel Iterative-Recursive Karatsuba multiplier. The results of Vertix-5 FPGA implementation with full CLB based design is presented in this paper. The processor performs point multiplication for NIST recommended curve P256 and is based on an extended NIST reduction scheme. Our processor performs single point multiplication where points are represented in affine coordinates within 6.67 ms and runs at maximum frequency of 66.3 MHz. The design of our processor is entirely based on CLB blocks as opposed to other FPGA implementations.

Original languageBritish English
Title of host publication2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages493-496
Number of pages4
ISBN (Print)9781479924523
DOIs
StatePublished - 2013
Event2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 - Abu Dhabi, United Arab Emirates
Duration: 8 Dec 201311 Dec 2013

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period8/12/1311/12/13

Keywords

  • Elliptic Curve Cryptography
  • FPGA
  • Karatsuba-Ofman Multiplication
  • Redundant Signed Digit

Fingerprint

Dive into the research topics of 'An FPGA implementation of NIST 256 prime field ECC processor'. Together they form a unique fingerprint.

Cite this