@inproceedings{323d66ee23f046759b3713f45a681312,
title = "An FPGA implementation of NIST 256 prime field ECC processor",
abstract = "In this paper, we propose a new Application Specific Instruction-set (ASIP) ECC processor based on Redundant Signed Digit representation with a novel Iterative-Recursive Karatsuba multiplier. The results of Vertix-5 FPGA implementation with full CLB based design is presented in this paper. The processor performs point multiplication for NIST recommended curve P256 and is based on an extended NIST reduction scheme. Our processor performs single point multiplication where points are represented in affine coordinates within 6.67 ms and runs at maximum frequency of 66.3 MHz. The design of our processor is entirely based on CLB blocks as opposed to other FPGA implementations.",
keywords = "Elliptic Curve Cryptography, FPGA, Karatsuba-Ofman Multiplication, Redundant Signed Digit",
author = "H. Marzouqi and M. Al-Qutayri and K. Salah",
year = "2013",
doi = "10.1109/ICECS.2013.6815461",
language = "British English",
isbn = "9781479924523",
series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "493--496",
booktitle = "2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013",
address = "United States",
note = "2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 ; Conference date: 08-12-2013 Through 11-12-2013",
}