TY - GEN
T1 - An FPGA accelerator for hash tree generation in the Merkle Signature Scheme
AU - Shoufan, Abdulhadi
PY - 2010
Y1 - 2010
N2 - Merkle Signature Scheme relies on secure hash functions and is, therefore, assumed to be resistant to attacks by quantum computers. The generation of the Merkle public key, however, is highly time-consuming because of the huge number of hash operations required to set up a complete hash tree. Fortunately, setting up such trees features inherent parallelism, which may be utilized for accelerating this process using a specific hardware platform. This paper presents a flexible and efficient hardware architecture on an FPGA platform to accelerate the generation of Merkle hash trees. Timing measurements on a prototype with different parameters show a considerable performance boost compared to a similar software solution.
AB - Merkle Signature Scheme relies on secure hash functions and is, therefore, assumed to be resistant to attacks by quantum computers. The generation of the Merkle public key, however, is highly time-consuming because of the huge number of hash operations required to set up a complete hash tree. Fortunately, setting up such trees features inherent parallelism, which may be utilized for accelerating this process using a specific hardware platform. This paper presents a flexible and efficient hardware architecture on an FPGA platform to accelerate the generation of Merkle hash trees. Timing measurements on a prototype with different parameters show a considerable performance boost compared to a similar software solution.
UR - http://www.scopus.com/inward/record.url?scp=77951275502&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-12133-3_15
DO - 10.1007/978-3-642-12133-3_15
M3 - Conference contribution
AN - SCOPUS:77951275502
SN - 3642121322
SN - 9783642121326
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 145
EP - 156
BT - Reconfigurable Computing
T2 - 6th International Symposium on Applied Reconfigurable Computing, ARC 2010
Y2 - 17 March 2010 through 19 March 2010
ER -