@inproceedings{a23c816f4bd1428b8996761f0daec216,
title = "An efficient partitioning algorithm of combinational CMOS circuits",
abstract = "This paper presents an efficient algorithm to partition combinational CMOS circuits for pseudoexhaustive testing. We present the effect of the partitioning algorithm on critical paths. Our objective is to reduce the delay penalty of test cell insertion for pseudoexhaustive testing. Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to test all of its individual cones. Our testing ensures detection of all nonredundant combinational faults. We have developed an optimization process that can be used to find the optimal size of primary input cone (N) and fanout (F) values, to be used for partitioning a given circuit. In our work, the designer can choose between the fewest number of partitioning points and the least delay in critical path. ISCAS'85 benchmark circuits have been successfully partitioned, and when our results are compared to other partitioning methods, our algorithm makes fewer partitions.",
keywords = "Circuit faults, Circuit testing, CMOS integrated circuits, CMOS technology, Delay, Electrical fault detection, Fault detection, Partitioning algorithms, Statistical analysis, Very large scale integration",
author = "B. Shaer and K. Dib",
note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2002 ; Conference date: 25-04-2002 Through 26-04-2002",
year = "2002",
doi = "10.1109/ISVLSI.2002.1016890",
language = "British English",
series = "Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI",
publisher = "IEEE Computer Society",
pages = "159--164",
editor = "Asim Smailagic and Robert Brodersen",
booktitle = "Proceedings - IEEE Computer Society Annual Symposium on VLSI",
address = "United States",
}