An adaptive CFAR embedded system architecture for target detection

Ridha Djemal, Kais Belwafi, Saleh Alshebeili

    Research output: Contribution to journalArticlepeer-review

    5 Scopus citations


    This paper presents field-programmable gate array (FPGA)-based novel forward and backward automatic censored cell algorithms using a Nios II core processor embedded on a Stratix II FPGA programmable device. These algorithms were recently presented for target detection in a nonhomogeneous environment, and they operate in a complementary manner to allow for high-resolution target detection with a time constraint fixed below 0.5 μs. The ACOSD-based constant false alarm rate detector does not require any prior information regarding the background environment and employs statistical analysis to dynamically calculate the threshold at which the ordered cells under investigation are accepted or rejected. The advantages of the proposed system lie in its simplicity and short processing time while maintaining a low development cost. For a reference window of 16 range cells, the experimental results obtained using the Stratix II development kit demonstrate that the proposed architecture works properly with a processing speed of 100 MHz and an overall detector execution time of 0.11 μs for each range cell. The designed hardware, which is an example of system-on-chip architecture, was physically realized in a Stratix II FPGA device, and the results are presented and discussed.

    Original languageBritish English
    Pages (from-to)109-127
    Number of pages19
    JournalDesign Automation for Embedded Systems
    Issue number1
    StatePublished - Mar 2013


    • Constant false alarm rate
    • Radar system
    • Real-time system
    • System on chip


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