Alternative architectures for the 2-D DCT algorithm

Chrissavgi Dre; Anna Tatsaki; Thanos Stouraitis; Costas Goutis

Alternative architectures for the 2-D DCT algorithm

Chrissavgi Dre, Anna Tatsaki, Thanos Stouraitis, Costas Goutis

Electrical Engineering

University of Patras

Research output: Contribution to journal › Conference article › peer-review

Abstract

Recently, a new fast algorithm has been proposed for the computation of the 2-D N × N-point Discrete Cosine Transform, where N is decomposed into two mutually prime numbers N₁ and N₂, [4]. Using Prime-Factor Decomposition (PFD) and appropriate index mappings, the algorithm results in fewer multiplications than other fast 2-D DCT algorithms. In this paper, a methodology for systematic mapping of this algorithm onto hardware is presented. The proposed methodology reveals the existence of a few connected components in the signal-flow graph (SFG) of the algorithm and leads to architectures that can be systematically derived and exhibit varying throughput and hardware complexity.

Original language	British English
Pages (from-to)	2156-2159
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
State	Published - 1995
Event	Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA Duration: 30 Apr 1995 → 3 May 1995

Cite this

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title = "Alternative architectures for the 2-D DCT algorithm",

abstract = "Recently, a new fast algorithm has been proposed for the computation of the 2-D N × N-point Discrete Cosine Transform, where N is decomposed into two mutually prime numbers N1 and N2, [4]. Using Prime-Factor Decomposition (PFD) and appropriate index mappings, the algorithm results in fewer multiplications than other fast 2-D DCT algorithms. In this paper, a methodology for systematic mapping of this algorithm onto hardware is presented. The proposed methodology reveals the existence of a few connected components in the signal-flow graph (SFG) of the algorithm and leads to architectures that can be systematically derived and exhibit varying throughput and hardware complexity.",

author = "Chrissavgi Dre and Anna Tatsaki and Thanos Stouraitis and Costas Goutis",

year = "1995",

language = "British English",

volume = "3",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) ; Conference date: 30-04-1995 Through 03-05-1995",

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T1 - Alternative architectures for the 2-D DCT algorithm

AU - Dre, Chrissavgi

AU - Tatsaki, Anna

AU - Stouraitis, Thanos

AU - Goutis, Costas

PY - 1995

Y1 - 1995

N2 - Recently, a new fast algorithm has been proposed for the computation of the 2-D N × N-point Discrete Cosine Transform, where N is decomposed into two mutually prime numbers N1 and N2, [4]. Using Prime-Factor Decomposition (PFD) and appropriate index mappings, the algorithm results in fewer multiplications than other fast 2-D DCT algorithms. In this paper, a methodology for systematic mapping of this algorithm onto hardware is presented. The proposed methodology reveals the existence of a few connected components in the signal-flow graph (SFG) of the algorithm and leads to architectures that can be systematically derived and exhibit varying throughput and hardware complexity.

AB - Recently, a new fast algorithm has been proposed for the computation of the 2-D N × N-point Discrete Cosine Transform, where N is decomposed into two mutually prime numbers N1 and N2, [4]. Using Prime-Factor Decomposition (PFD) and appropriate index mappings, the algorithm results in fewer multiplications than other fast 2-D DCT algorithms. In this paper, a methodology for systematic mapping of this algorithm onto hardware is presented. The proposed methodology reveals the existence of a few connected components in the signal-flow graph (SFG) of the algorithm and leads to architectures that can be systematically derived and exhibit varying throughput and hardware complexity.

UR - http://www.scopus.com/inward/record.url?scp=0029205168&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0029205168

SN - 0271-4310

VL - 3

SP - 2156

EP - 2159

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)

Y2 - 30 April 1995 through 3 May 1995

ER -

Alternative architectures for the 2-D DCT algorithm

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