Adaptive zero-crossing digital phase-locked loop for packet synchronization

Saleh R. Al-Araji; Ehab Salahat; Dima Kilani; Shahd Abu Yasin; Heba Alkhoja; James Aweya

doi:10.1109/NEWCAS.2013.6573607

Adaptive zero-crossing digital phase-locked loop for packet synchronization

Saleh R. Al-Araji, Ehab Salahat, Dima Kilani, Shahd Abu Yasin, Heba Alkhoja, James Aweya

Emirates ICT Innovation Center

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

This paper describes the design and performance analysis of a new approach for frequencysynchronization and transfer over packet networks. The proposed system utilizestimestamps-based with raised cosine pulse shaping first order adaptive zero-crossing digital phase-locked loop (AZC-DPLL). The system is designedto recover frequency as well as packets, independently of the input signal level in the presence of noise. This technique provides reliable locking by adjusting the loop gain, with the aid of finite state machine (FSM), and hence both system locking range and acquisition are improved.

Original language	British English
Title of host publication	2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
DOIs	https://doi.org/10.1109/NEWCAS.2013.6573607
State	Published - 2013
Event	2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013 - Paris, France Duration: 16 Jun 2013 → 19 Jun 2013

Publication series

Name	2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013

Conference

Conference	2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
Country/Territory	France
City	Paris
Period	16/06/13 → 19/06/13

Keywords

Digital Phase-locked Loops
Packet Network
Raised Cosine Pulse Shaping
Synchronization
Zero crossing Digital Phase lock loops

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10.1109/NEWCAS.2013.6573607

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Al-Araji, S. R., Salahat, E., Kilani, D., Yasin, S. A., Alkhoja, H., & Aweya, J. (2013). Adaptive zero-crossing digital phase-locked loop for packet synchronization. In 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013 Article 6573607 (2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013). https://doi.org/10.1109/NEWCAS.2013.6573607

@inproceedings{456bb5ad057843a5869a5f96cbf05ac4,

title = "Adaptive zero-crossing digital phase-locked loop for packet synchronization",

abstract = "This paper describes the design and performance analysis of a new approach for frequencysynchronization and transfer over packet networks. The proposed system utilizestimestamps-based with raised cosine pulse shaping first order adaptive zero-crossing digital phase-locked loop (AZC-DPLL). The system is designedto recover frequency as well as packets, independently of the input signal level in the presence of noise. This technique provides reliable locking by adjusting the loop gain, with the aid of finite state machine (FSM), and hence both system locking range and acquisition are improved.",

keywords = "Digital Phase-locked Loops, Packet Network, Raised Cosine Pulse Shaping, Synchronization, Zero crossing Digital Phase lock loops",

author = "Al-Araji, {Saleh R.} and Ehab Salahat and Dima Kilani and Yasin, {Shahd Abu} and Heba Alkhoja and James Aweya",

year = "2013",

doi = "10.1109/NEWCAS.2013.6573607",

language = "British English",

isbn = "9781479906185",

series = "2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013",

booktitle = "2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013",

note = "2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013 ; Conference date: 16-06-2013 Through 19-06-2013",

}

Al-Araji, SR, Salahat, E, Kilani, D, Yasin, SA, Alkhoja, H & Aweya, J 2013, Adaptive zero-crossing digital phase-locked loop for packet synchronization. in 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013., 6573607, 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013, Paris, France, 16/06/13. https://doi.org/10.1109/NEWCAS.2013.6573607

Adaptive zero-crossing digital phase-locked loop for packet synchronization. / Al-Araji, Saleh R.; Salahat, Ehab; Kilani, Dima et al.
2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013. 2013. 6573607 (2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Adaptive zero-crossing digital phase-locked loop for packet synchronization

AU - Al-Araji, Saleh R.

AU - Salahat, Ehab

AU - Kilani, Dima

AU - Yasin, Shahd Abu

AU - Alkhoja, Heba

AU - Aweya, James

PY - 2013

Y1 - 2013

N2 - This paper describes the design and performance analysis of a new approach for frequencysynchronization and transfer over packet networks. The proposed system utilizestimestamps-based with raised cosine pulse shaping first order adaptive zero-crossing digital phase-locked loop (AZC-DPLL). The system is designedto recover frequency as well as packets, independently of the input signal level in the presence of noise. This technique provides reliable locking by adjusting the loop gain, with the aid of finite state machine (FSM), and hence both system locking range and acquisition are improved.

AB - This paper describes the design and performance analysis of a new approach for frequencysynchronization and transfer over packet networks. The proposed system utilizestimestamps-based with raised cosine pulse shaping first order adaptive zero-crossing digital phase-locked loop (AZC-DPLL). The system is designedto recover frequency as well as packets, independently of the input signal level in the presence of noise. This technique provides reliable locking by adjusting the loop gain, with the aid of finite state machine (FSM), and hence both system locking range and acquisition are improved.

KW - Digital Phase-locked Loops

KW - Packet Network

KW - Raised Cosine Pulse Shaping

KW - Synchronization

KW - Zero crossing Digital Phase lock loops

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U2 - 10.1109/NEWCAS.2013.6573607

DO - 10.1109/NEWCAS.2013.6573607

M3 - Conference contribution

AN - SCOPUS:84883477142

SN - 9781479906185

T3 - 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013

BT - 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013

T2 - 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013

Y2 - 16 June 2013 through 19 June 2013

ER -

Adaptive zero-crossing digital phase-locked loop for packet synchronization

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Keywords

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