Adaptive zero-crossing digital phase-locked loop for packet synchronization

Saleh R. Al-Araji, Ehab Salahat, Dima Kilani, Shahd Abu Yasin, Heba Alkhoja, James Aweya

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

This paper describes the design and performance analysis of a new approach for frequencysynchronization and transfer over packet networks. The proposed system utilizestimestamps-based with raised cosine pulse shaping first order adaptive zero-crossing digital phase-locked loop (AZC-DPLL). The system is designedto recover frequency as well as packets, independently of the input signal level in the presence of noise. This technique provides reliable locking by adjusting the loop gain, with the aid of finite state machine (FSM), and hence both system locking range and acquisition are improved.

Original languageBritish English
Title of host publication2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
DOIs
StatePublished - 2013
Event2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013 - Paris, France
Duration: 16 Jun 201319 Jun 2013

Publication series

Name2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013

Conference

Conference2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
Country/TerritoryFrance
CityParis
Period16/06/1319/06/13

Keywords

  • Digital Phase-locked Loops
  • Packet Network
  • Raised Cosine Pulse Shaping
  • Synchronization
  • Zero crossing Digital Phase lock loops

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