@inproceedings{f0e437050146462ca74ebb613d33ce58,
title = "Adaptive TDTL with enhanced performance using sample sensing technique",
abstract = "This paper proposes an adaptive time delay digital tanlock Loop architecture with enhanced performance. The new loop includes an error-sensing block that monitors the sample values in the delayed path and subsequently adjusts the digital filter gain before the system goes out of lock Simulation and FPGA implementation show that the loop can efficiently handle large frequency disturbances that may otherwise result in out of lock conditions.",
author = "Saleh Al-Araji and Mahmoud Al-Qutayri and Abdullah Al-Zaabi",
year = "2006",
language = "British English",
isbn = "0780393902",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
pages = "5700--5703",
booktitle = "ISCAS 2006",
note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",
}