Adaptive TDTL with enhanced performance using sample sensing technique

Saleh Al-Araji, Mahmoud Al-Qutayri, Abdullah Al-Zaabi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper proposes an adaptive time delay digital tanlock Loop architecture with enhanced performance. The new loop includes an error-sensing block that monitors the sample values in the delayed path and subsequently adjusts the digital filter gain before the system goes out of lock Simulation and FPGA implementation show that the loop can efficiently handle large frequency disturbances that may otherwise result in out of lock conditions.

Original languageBritish English
Title of host publicationISCAS 2006
Subtitle of host publication2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages5700-5703
Number of pages4
StatePublished - 2006
EventISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece
Duration: 21 May 200624 May 2006

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

ConferenceISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/TerritoryGreece
CityKos
Period21/05/0624/05/06

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