Adaptive low-pass filter based DC offset removal technique for three-phase plls

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Abstract

The presence of dc offset in the inputs of a phase-locked loop (PLL) introduces fundamental frequency oscillations in the estimated quantities. Due to their low frequency in a synchronous reference frame, removal of these oscillations is a challenging task. Recent design studies of pre/in-loop filtering based advanced PLLs show that incorporation of dc offset removal in a filtering stage reduces the bandwidth of the PLL. This degrades the dynamic performance of the PLL and results in slower response time. To tackle this issue, a simple yet effective dc offset removal technique based on adaptive low-pass filters is introduced in this letter. The proposed technique can be applied as an add-on to any PLL structures without altering their design. Therefore, its application has a minimal effect on the dynamic performance of the PLL under study. The effectiveness of the proposed technique is evaluated experimentally by applying it to different PLL structures.

Original languageBritish English
Pages (from-to)9025-9029
Number of pages5
JournalIEEE Transactions on Industrial Electronics
Volume65
Issue number11
DOIs
StatePublished - Nov 2018

Keywords

  • Disturbance rejection
  • feedback control system
  • frequency-locked loop
  • stability
  • synchronous reference frame phase-locked loop (SRF-PLL)

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