TY - JOUR
T1 - A web-based visualization and animation platform for digital logic design
AU - Shoufan, Abdulhadi
AU - Lu, Zheng
AU - Huss, Sorin A.
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2015/4/1
Y1 - 2015/4/1
N2 - This paper presents a web-based education platform for the visualization and animation of the digital logic design process. This includes the design of combinatorial circuits using logic gates, multiplexers, decoders, and look-up-tables as well as the design of finite state machines. Various configurations of finite state machines can be selected to define the machine type, the state code, and the flip-flop type. Logic minimization with the K-map approach and the Quine McCluskey scheme is also supported. The tools, denoted as DLD-VISU, help students practice related topics in digital logic design courses. Also, instructors can use the tools to efficiently generate and verify examples for lecture notes or for homework problems and assignments. DLD-VISU was designed relying on a thorough investigation of related pedagogical aspects to define appropriate interactive graphical processes. The decision for a web-based solution, on the one hand, was motivated by making the tools available, portable, expandable, and at the same time transparent to the user. On the other hand, the advocated approach enables instructors to define access rules for their students to assure that students cannot use the tools to solve assessed homework problems or assignments before submission deadline. DLD-VISU supports self-assessment and reflects the student learning process using learning curves. The proposed platform was evaluated both in form of students' feedback as well as by analyzing the impact of using the tools on students' performance.
AB - This paper presents a web-based education platform for the visualization and animation of the digital logic design process. This includes the design of combinatorial circuits using logic gates, multiplexers, decoders, and look-up-tables as well as the design of finite state machines. Various configurations of finite state machines can be selected to define the machine type, the state code, and the flip-flop type. Logic minimization with the K-map approach and the Quine McCluskey scheme is also supported. The tools, denoted as DLD-VISU, help students practice related topics in digital logic design courses. Also, instructors can use the tools to efficiently generate and verify examples for lecture notes or for homework problems and assignments. DLD-VISU was designed relying on a thorough investigation of related pedagogical aspects to define appropriate interactive graphical processes. The decision for a web-based solution, on the one hand, was motivated by making the tools available, portable, expandable, and at the same time transparent to the user. On the other hand, the advocated approach enables instructors to define access rules for their students to assure that students cannot use the tools to solve assessed homework problems or assignments before submission deadline. DLD-VISU supports self-assessment and reflects the student learning process using learning curves. The proposed platform was evaluated both in form of students' feedback as well as by analyzing the impact of using the tools on students' performance.
UR - http://www.scopus.com/inward/record.url?scp=84933050086&partnerID=8YFLogxK
U2 - 10.1109/TLT.2014.2356464
DO - 10.1109/TLT.2014.2356464
M3 - Article
AN - SCOPUS:84933050086
SN - 1939-1382
VL - 8
SP - 225
EP - 239
JO - IEEE Transactions on Learning Technologies
JF - IEEE Transactions on Learning Technologies
IS - 2
M1 - 6897963
ER -