A VLSI design methodology for RNS full adder-based inner product architectures

D. J. Soudris, V. Paliouras, T. Stouraitis, C. E. Goutis

Research output: Contribution to journalArticlepeer-review

21 Scopus citations

Abstract

In this paper, a systematic graph-based methodology for synthesizing VLSI RNS architectures using full adders as the basic building block is introduced. The design methodology derives array architectures starting from the algorithm level and ending up with the bit-level design. Using as target architectural style the regular array processor, the proposed procedure constructs the two-dimensional (2-D) dependence graph of the bit-level algorithm, which is formally described by sets of uniform recurrent equations. The main characteristic of the proposed architectures is that they can operate at very high-throughput rates. The proposed architectures exhibit significantly reduced complexity than ROM-based ones.

Original languageBritish English
Pages (from-to)315-318
Number of pages4
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume44
Issue number4
DOIs
StatePublished - 1997

Keywords

  • Bit-level design methodology
  • Inner-product processor
  • Residue number system

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