@inproceedings{0894827232f849718cb2eb30c9fec0b4,
title = "A VLSI architecture for fast and accurate floating-point sine/cosine evaluation",
abstract = "A VLSI architecture for fast and accurate floatingpoint sine/cosine evaluation is presented, combining floating-point and simple fixed-point arithmetic. The algorithm implemented by the architecture is based on second-order polynomial interpolation. The exploitation of certain properties of the trigonometric functions and of specific bit patterns which appear in the involved computations, has led to a 40% memory size reduction and low overall hardware complexity. The time required to evaluate a sine is less than the time required for three singleprecision floating-point MACs, while the computed sines and cosines are guaranteed to be accurate to half an ulp (unit in last position).",
author = "V. Paliouras and K. Karagianni and T. Stouraitis",
note = "Publisher Copyright: {\textcopyright} 1998 IEEE.; 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 ; Conference date: 07-09-1998 Through 10-09-1998",
year = "1998",
doi = "10.1109/ICECS.1998.813365",
language = "British English",
series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "473--476",
booktitle = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",
address = "United States",
}