TY - JOUR
T1 - A Type-3 PLL for Single-Phase Applications
AU - Bamigbade, Abdullahi
AU - Khadkikar, Vinod
AU - Hosani, Mohamed Al
N1 - Funding Information:
Manuscript received February 9, 2020; revised April 11, 2020; accepted May 19, 2020. Date of publication June 2, 2020; date of current version September 18, 2020. This work was supported by the Masdar Institute (now Khalifa University), Abu Dhabi, UAE under Cooperative Agreement between the Masdar Institute and the Massachusetts Institute of Technology (MIT), Cambridge, MA, USA— Reference 02/MI/MIT/CP/11/07633/GEN/G/00. (Corresponding author: Vinod Khadkikar.) Abdullahi Bamigbade and Vinod Khadkikar are with Advanced Power and Energy Center, Electrical Engineering and Computer Science Department, Khalifa University, Abu Dhabi 127788, UAE (e-mail: abdullahi.bamigbade@ ku.ac.ae; [email protected]).
Publisher Copyright:
© 1972-2012 IEEE.
PY - 2020/9/1
Y1 - 2020/9/1
N2 - This article proposes an effective solution by means of gain and phase-lead compensations to overcome the challenges of instability and slow dynamic performance exhibited by single-phase type-3 phase-locked loops (PLLs). By considering a single-phase second-order generalized integrator based type-3 PLL, a detailed design guideline is provided in choosing the PLL's parameters. Stability analysis of the designed PLL reveals that its finite gain margin causes PLL instability under severe voltage dip, while its limited phase margin results in poor dynamics. Therefore, gain compensation is carried out within a limited region such that the PLL's stability limit is not exceeded, while phase-lead compensation is employed to enhance the PLL's damping. When both modifications are incorporated within the PLL loop, the PLL's speed of estimation is improved significantly when compared with those of existing solutions applied to type-3 PLLs and the response obtained is comparable to that of a type-2 PLL. The performance evaluation of the proposed solution is carried out by experimental comparison with a standard single-phase type-3 PLL, a type-3 PLL with the amplitude normalization system, a phase feed-forward type-3 PLL, a dual-loop type-3 PLL, and a type-2 PLL.
AB - This article proposes an effective solution by means of gain and phase-lead compensations to overcome the challenges of instability and slow dynamic performance exhibited by single-phase type-3 phase-locked loops (PLLs). By considering a single-phase second-order generalized integrator based type-3 PLL, a detailed design guideline is provided in choosing the PLL's parameters. Stability analysis of the designed PLL reveals that its finite gain margin causes PLL instability under severe voltage dip, while its limited phase margin results in poor dynamics. Therefore, gain compensation is carried out within a limited region such that the PLL's stability limit is not exceeded, while phase-lead compensation is employed to enhance the PLL's damping. When both modifications are incorporated within the PLL loop, the PLL's speed of estimation is improved significantly when compared with those of existing solutions applied to type-3 PLLs and the response obtained is comparable to that of a type-2 PLL. The performance evaluation of the proposed solution is carried out by experimental comparison with a standard single-phase type-3 PLL, a type-3 PLL with the amplitude normalization system, a phase feed-forward type-3 PLL, a dual-loop type-3 PLL, and a type-2 PLL.
KW - Dynamic performance
KW - gain margin (GM)
KW - loop filter (LF)
KW - phase margin
KW - phase-locked loop (PLL)
KW - stability
KW - steady-state error
UR - http://www.scopus.com/inward/record.url?scp=85091750293&partnerID=8YFLogxK
U2 - 10.1109/TIA.2020.2999435
DO - 10.1109/TIA.2020.2999435
M3 - Article
AN - SCOPUS:85091750293
SN - 0093-9994
VL - 56
SP - 5533
EP - 5542
JO - IEEE Transactions on Industry Applications
JF - IEEE Transactions on Industry Applications
IS - 5
M1 - 9106750
ER -