@inproceedings{398a97bc3be6463bb1535a9a96183c9c,
title = "A robust histogram-based image segmentation ASIC design for System-on-Chip using 65nm technology",
abstract = "Image segmentation is an essential preprocessing step for many computer vision and image processing applications. Implementing algorithms that handle such images in hardware will speed up the processing task considerably. In this paper, a new robust histogram-based image segmentation ASIC design of a System-on-Chip (SoC) using 65nm technology is presented. With a clock frequency of 289 MHz, the SoC can reach a frame rate of a 4410 FPS for an image resolution of 256×256. This is few order of magnitudes faster than the FPGA implementation in the literature. The finished-chip details renders it suitable for realtime and mobile applications.",
keywords = "ASIC, Histogram-based thresholding, Image processing, Image segmentation, Real-time, System-on-chip",
author = "Ehab Salahat and Hani Saleh and {Sami Zitouni}, M. and Andrzej Sluzek and Baker Mohammad and Mahmoud Al-Qutayri and Mohammad Ismail",
note = "Funding Information: Funding was provided by the Ghent University Multidisciplinary Research Partnership {\textquoteleft}Bioinformatics: from nucleotides to networks{\textquoteright}. Publisher Copyright: {\textcopyright} 2015 IEEE.",
year = "2015",
month = apr,
day = "6",
doi = "10.1109/ICCSPA.2015.7081298",
language = "British English",
series = "2015 International Conference on Communications, Signal Processing, and Their Applications, ICCSPA 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 International Conference on Communications, Signal Processing, and Their Applications, ICCSPA 2015",
address = "United States",
}