A robust histogram-based image segmentation ASIC design for System-on-Chip using 65nm technology

Ehab Salahat, Hani Saleh, M. Sami Zitouni, Andrzej Sluzek, Baker Mohammad, Mahmoud Al-Qutayri, Mohammad Ismail

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Image segmentation is an essential preprocessing step for many computer vision and image processing applications. Implementing algorithms that handle such images in hardware will speed up the processing task considerably. In this paper, a new robust histogram-based image segmentation ASIC design of a System-on-Chip (SoC) using 65nm technology is presented. With a clock frequency of 289 MHz, the SoC can reach a frame rate of a 4410 FPS for an image resolution of 256×256. This is few order of magnitudes faster than the FPGA implementation in the literature. The finished-chip details renders it suitable for realtime and mobile applications.

Original languageBritish English
Title of host publication2015 International Conference on Communications, Signal Processing, and Their Applications, ICCSPA 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479965328
DOIs
StatePublished - 6 Apr 2015

Publication series

Name2015 International Conference on Communications, Signal Processing, and Their Applications, ICCSPA 2015

Keywords

  • ASIC
  • Histogram-based thresholding
  • Image processing
  • Image segmentation
  • Real-time
  • System-on-chip

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