A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory

This paper presents a new read and write assist technique to enable lower voltage operation for Static Random Access Memory (SRAM). The ability to scale the operating voltage with frequency of the chip has big impact on power consumption (Pαv ²). The lower end of the operating voltage (V _ddmin) for most chips is determined by the stability of the SRAM cell. The new technique uses a contention-free circuit to generate a Reduced Voltage Swing (RVS) on the wordline (VWL) and selectively reduce the supply to the bitcell (V _ddmem) during write. The required VWL and bitcell voltages are programmable and controllable to adapt to performance and yield requirements. An 8 KB memory test-chip was designed to demonstrate this technique in a low-leakage 45 nm process technology. Results show a 7 to 19% improvement in V _ddmin depending on the process corner, which translates into 1440% reduction on active power. The proposed technique has 4% area overhead and minimal impact to speed.