A Re-configurable Memristor Array Structure for In-Memory Computing Applications

Yasmin Halawani, Baker Mohammad, Mahmoud Al-Qutayri, Said Al-Sarawi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

The memristor-based array architecture promises an efficient analog implementation of the multiply-add engine that can have significant impact in signal processing and neural network implementations. The ability to represent a negative conductance value to correspond to a negative matrix element is one of the main challenges associated with analog memristor array implementation. In this paper, a re-configurable general purpose single array architecture is proposed to realize a multiply-add operation that allows both positive and negative conductance values. The architecture utilizes memristor devices with two different characteristics, one for computation and one for storage. The proposed design has been verified using LTSpice circuit simulator. Several cases with different combinations of polarities for the input voltage and conductance values were demonstrated.

Original languageBritish English
Title of host publicationProceeding of 2018 30th International Conference on Microelectronics, ICM 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages160-163
Number of pages4
ISBN (Electronic)9781538681671
DOIs
StatePublished - 2 Jul 2018
Event30th International Conference on Microelectronics, ICM 2018 - Sousse, Tunisia
Duration: 16 Dec 201819 Dec 2018

Publication series

NameProceedings of the International Conference on Microelectronics, ICM
Volume2018-December

Conference

Conference30th International Conference on Microelectronics, ICM 2018
Country/TerritoryTunisia
CitySousse
Period16/12/1819/12/18

Keywords

  • analog inmemory computing
  • Memristor
  • multiply-add
  • negative conductance
  • neural network

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