TY - GEN
T1 - A pulsed decimal technique for single-channel, dynamic signaling for IoT applications
AU - Muzaffar, Shahzad
AU - Elfadel, Ibrahim M.
N1 - Funding Information:
ACKNOWLEDGMENTS This work has been supported by the Semiconductor Research Corporation (SRC) under the Abu Dhabi-SRC Center of Excellence on Energy-Efficient Electronic Systems (ACE4S), Contract 2013 HJ2440, with customized funding from the Mubadala Investment Company, Abu Dhabi, UAE.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/12/13
Y1 - 2017/12/13
N2 - Pulsed-Index Communication (PIC) is a recent technique for single-channel communication which is based on the principle of transferring the indices of only the ON bits in the form of a series of pulse streams. In this paper, we present a modified version of PIC which is based on the same underlying idea but with key improvements in data rate and reliability. The proposed technique is called Pulsed Decimal Communication (PDC). Like PIC, PDC is a protocol for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It however achieves higher data rates by introducing a three-step algorithm, comprising a segmentation, an encoding, and a sub-segmentation step. The segmentation step is used to split the data word into smaller segments and therefore smaller decimal numbers to represent them. The encoding step reduces the number of ON bits in the data and relocates them to lower indices. The sub-segmentation step is used to split further the segments into smaller sub-segments. The complete process reduces the number of pulses required to transmit binary data, thus improving the data rate. Compared with PIC, PDC achieves a 78% improvement in data rate and is more reliable as it eliminates the variations in the number of symbols to be transmitted. An FPGA and an ASIC (65nm technology) implementation of the protocol show that the low-power operation and small footprint of PIC are maintained in PDC, which consumes around 25of power at a clock frequency of 25MHz with a gate count of approximately 2150.
AB - Pulsed-Index Communication (PIC) is a recent technique for single-channel communication which is based on the principle of transferring the indices of only the ON bits in the form of a series of pulse streams. In this paper, we present a modified version of PIC which is based on the same underlying idea but with key improvements in data rate and reliability. The proposed technique is called Pulsed Decimal Communication (PDC). Like PIC, PDC is a protocol for single-channel, high-data rate, low-power dynamic signaling that does not require any clock and data recovery. It however achieves higher data rates by introducing a three-step algorithm, comprising a segmentation, an encoding, and a sub-segmentation step. The segmentation step is used to split the data word into smaller segments and therefore smaller decimal numbers to represent them. The encoding step reduces the number of ON bits in the data and relocates them to lower indices. The sub-segmentation step is used to split further the segments into smaller sub-segments. The complete process reduces the number of pulses required to transmit binary data, thus improving the data rate. Compared with PIC, PDC achieves a 78% improvement in data rate and is more reliable as it eliminates the variations in the number of symbols to be transmitted. An FPGA and an ASIC (65nm technology) implementation of the protocol show that the low-power operation and small footprint of PIC are maintained in PDC, which consumes around 25of power at a clock frequency of 25MHz with a gate count of approximately 2150.
UR - https://www.scopus.com/pages/publications/85047555240
U2 - 10.1109/VLSI-SoC.2017.8203491
DO - 10.1109/VLSI-SoC.2017.8203491
M3 - Conference contribution
AN - SCOPUS:85047555240
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
BT - 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
PB - IEEE Computer Society
T2 - 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
Y2 - 23 October 2017 through 25 October 2017
ER -