Abstract
This paper presents a novel list-scheduling algorithm for low-energy software execution. The aim of the instruction scheduling is the minimization of the inter-instruction energy costs that are due to the switching activity of the processor circuit. The input of the scheduling algorithm is the original code sequence. Its output is a re-arranged sequence of the same instructions that minimizes the total interinstruction effect cost and that has no impact on the program functionality. The inter-instruction effect cost is determined by means of physical measurements. The target architecture has been the ARM7TDMI processor core. The results of the optimization algorithm have been validated upon the implementation of the IEEE 802.11 protocol microcode for wireless local area networks.
| Original language | British English |
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| Pages (from-to) | IV/97-IV/100 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| State | Published - 2002 |
| Event | 2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: 26 May 2002 → 29 May 2002 |