A novel hardware/software embedded system based on automatic censored target detection for radar systems

Ridha Djemal, Kais Belwafi, Walid Kaaniche, Saleh A. Alshebeili

    Research output: Contribution to journalArticlepeer-review

    8 Scopus citations

    Abstract

    This paper presents a practical design exploration for a new application related to real-time, high-resolution target detection for radar systems. In this paper, an embedded architecture that combines the hardware and software components in a single platform is experienced using a field programmable gate array FPGA-based PC-board. The detection process utilises three techniques: namely, automatic censored ordered statistics detection (ACOSD), cell averaging (CA) and ordered statistics (OS) CFAR techniques, all of which operate in parallel to increase the accuracy of the detection and to reduce the false-alarm rate for both homogeneous and non-homogeneous environments. A prototype of the embedded system detector has been implemented for homogeneous and non-homogeneous environments on Stratix IV FPGA Board. The prototype operates at 200 MHz and performs real-time target detection with an execution delay of 0.27 μs, which is less than the critical time (0.5 μs) for high-resolution detection.

    Original languageBritish English
    Pages (from-to)301-312
    Number of pages12
    JournalAEU - International Journal of Electronics and Communications
    Volume67
    Issue number4
    DOIs
    StatePublished - 2013

    Keywords

    • CFAR
    • Co-design
    • Embedded system
    • FPGA
    • Radar

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