TY - JOUR
T1 - A New Type-2 PLL Based on Unit Delay Phase Angle Error Compensation during the Frequency Ramp
AU - Hamed, Hany A.
AU - El Moursi, Mohamed Shawky
N1 - Funding Information:
Manuscript received November 3, 2018; revised January 12, 2019 and March 22, 2019; accepted April 9, 2019. Date of publication April 15, 2019; date of current version June 18, 2019. This letter is based upon work supported by the Khalifa University of Science and Technology under Award No. CIRA-2018-37. Paper no. PESL-00240-2018. (Corresponding author: Hany A. Hamed.) H. A. Hamed is with the Department of Electrical and Automation Engineering, Emirates Steel, Abu Dhabi 9022, United Arab Emirates (e-mail: [email protected]).
Publisher Copyright:
© 1969-2012 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - This letter introduces a unit delay compensation scheme for Type-2 phase locked loop (Type-2 PLL) to eliminate the steady state phase angle error during the frequency ramp. The proposed PLL (ZPLL) uses an adaptive delayed signal cancellation (DSC) filter, along with a compensation scheme, to ensure effective operation under unbalanced grid. The proposed compensation scheme acts as an open-loop compensator, hence, ZPLL functions as Type-3 PLL with Type-2 dynamics features while preserving its second order characteristics. The proposed scheme is mathematically and experimentally validated under different scenarios of grid disturbances. The obtained results demonstrate the capability of the proposed compensation scheme to obtain a zero steady state phase angle error during the frequency ramp while employing symmetrical and asymmetrical voltage dip.
AB - This letter introduces a unit delay compensation scheme for Type-2 phase locked loop (Type-2 PLL) to eliminate the steady state phase angle error during the frequency ramp. The proposed PLL (ZPLL) uses an adaptive delayed signal cancellation (DSC) filter, along with a compensation scheme, to ensure effective operation under unbalanced grid. The proposed compensation scheme acts as an open-loop compensator, hence, ZPLL functions as Type-3 PLL with Type-2 dynamics features while preserving its second order characteristics. The proposed scheme is mathematically and experimentally validated under different scenarios of grid disturbances. The obtained results demonstrate the capability of the proposed compensation scheme to obtain a zero steady state phase angle error during the frequency ramp while employing symmetrical and asymmetrical voltage dip.
KW - frequency ramp
KW - phase locked loop (PLL)
UR - https://www.scopus.com/pages/publications/85067826359
U2 - 10.1109/TPWRS.2019.2911048
DO - 10.1109/TPWRS.2019.2911048
M3 - Article
AN - SCOPUS:85067826359
SN - 0885-8950
VL - 34
SP - 3289
EP - 3293
JO - IEEE Transactions on Power Systems
JF - IEEE Transactions on Power Systems
IS - 4
M1 - 8691417
ER -