A New SVPWM for a Hybrid-Level Three-Phase Inverter for Common Mode Voltage Mitigation

This article proposes a new space vector pulse width modulation (SVPWM) technique for a hybrid-level three-phase inverter. The new SVPWM minimizes the root mean square (rms) value, the dv/dt, and the number of transitions of the common mode voltage (CMV). This has been achieved by the optimal selection and sequence of space vectors in each region. Moreover, the self-balancing of the dc-link capacitor voltages of the hybrid-level inverter is mathematically and experimentally validated. Additionally, the performance of the new inverter with the new PWM will be evaluated and compared to the PWM introduced in the literature as well as several existing solutions. This comparison was conducted using both experimental methods and MATLAB simulations. At high modulation index, the proposed PWM has a 20.13% lower CMV, a 75% lower dv/dt of the CMV, a 50% lower number of CMV transitions, and the same inverter losses compared to the PWM introduced in the literature. Furthermore, it offers a 57.7% lower CMV compared to the PWM introduced in the literature at low modulation index. Extensive dynamic testing across various input voltages, modulation indices, and frequencies validates the proposed system's robust performance. Experimental evaluations with a PV grid system show a leakage current of 132 mA (compared to 229.6 mA in existing methods) and a total harmonic distortion (THD) of 2.01% (compared to 2.6%), confirming its effectiveness and superiority within IEC standards.